Simulation Results: uart

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.49 %
  • code
  • 91.68 %
  • assert
  • 98.56 %
  • func
  • 63.23 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.130s 693.198us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.640s 16.696us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.680s 18.090us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.290s 1086.963us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.900s 110.969us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.960s 134.452us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.680s 18.090us 1 1 100.00
uart_csr_aliasing 0.900s 110.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 23.930s 113116.916us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.130s 693.198us 1 1 100.00
uart_tx_rx 23.930s 113116.916us 1 1 100.00
parity_error 2 2 100.00
uart_intr 7.620s 9182.354us 1 1 100.00
uart_rx_parity_err 49.020s 65980.462us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 23.930s 113116.916us 1 1 100.00
uart_intr 7.620s 9182.354us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 31.930s 34533.805us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 23.470s 160398.879us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.990s 119262.787us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 7.620s 9182.354us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 7.620s 9182.354us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 7.620s 9182.354us 1 1 100.00
perf 1 1 100.00
uart_perf 360.170s 15342.515us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.520s 3152.030us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.520s 3152.030us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.530s 1643.458us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.770s 5079.185us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.980s 1465.815us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.180s 2063.633us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 262.480s 52814.378us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 342.730s 314717.340us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.760s 10.853us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 45.268us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.970s 336.626us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.970s 336.626us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.640s 16.696us 1 1 100.00
uart_csr_rw 0.680s 18.090us 1 1 100.00
uart_csr_aliasing 0.900s 110.969us 1 1 100.00
uart_same_csr_outstanding 0.920s 35.419us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.640s 16.696us 1 1 100.00
uart_csr_rw 0.680s 18.090us 1 1 100.00
uart_csr_aliasing 0.900s 110.969us 1 1 100.00
uart_same_csr_outstanding 0.920s 35.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.160s 265.691us 1 1 100.00
uart_tl_intg_err 1.260s 173.788us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.260s 173.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.530s 1761.800us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 51345870525478760137643365600525015254019230003879073230332452028911760652032 74
UVM_ERROR @ 198898187 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 199398192 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 202534587 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 202625497 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty