Simulation Results: adc_ctrl

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.63 %
  • code
  • 92.00 %
  • assert
  • 91.90 %
  • func
  • 12.99 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 85.90 %
  • toggle
  • 98.82 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 8.340s 5812.990us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.030s 1022.610us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.180s 422.786us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 3.280s 1009.631us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.040s 1105.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.120s 473.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.180s 422.786us 1 1 100.00
adc_ctrl_csr_aliasing 2.040s 1105.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.720s 526.586us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.670s 291.032us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.180s 474.138us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.950s 428.702us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.850s 498.902us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.870s 440.181us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.900s 284.523us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.900s 500.605us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.690s 5635.230us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 30.490s 44403.991us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 172.610s 108039.407us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 3.810s 3897.335us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.010s 304.714us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.640s 328.737us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.640s 764.156us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.640s 764.156us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.030s 1022.610us 1 1 100.00
adc_ctrl_csr_rw 1.180s 422.786us 1 1 100.00
adc_ctrl_csr_aliasing 2.040s 1105.801us 1 1 100.00
adc_ctrl_same_csr_outstanding 8.130s 4672.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.030s 1022.610us 1 1 100.00
adc_ctrl_csr_rw 1.180s 422.786us 1 1 100.00
adc_ctrl_csr_aliasing 2.040s 1105.801us 1 1 100.00
adc_ctrl_same_csr_outstanding 8.130s 4672.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 6.130s 7594.800us 1 1 100.00
adc_ctrl_tl_intg_err 12.120s 7683.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 12.120s 7683.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.330s 1004.081us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 763356513967722589147499834506111708331640577585095569072160975984072938192 386
UVM_INFO @ 526585591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 110563086775729704524872818336981486368507862889697313072194359169521669587469 386
UVM_INFO @ 291031853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 12971987519620680569084590645197753962944662321528766542023401322566421518765 386
UVM_INFO @ 474138207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 44428351597679521510451626623153196660749361505151644157787492817856996326719 386
UVM_INFO @ 428701735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 89071211306182212720906350525753880062635080018717585885266754938701371815540 386
UVM_INFO @ 498902451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 30257847411896040984397301702846614608081879821940812166945243677949499369427 386
UVM_INFO @ 440180888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 33997335492655295626304120977798627889580682788506481843399996373605656838220 386
UVM_INFO @ 500605493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 94339963141011997352495206927867272648917323268642497435128222072691749552945 386
UVM_INFO @ 284523142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 100415185410900297051419842152734016796421639703837510173313002257849551739892 406
UVM_INFO @ 1004081320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 98841266667567562181262222618541880068418106618549470153010789024206507847203 399
UVM_INFO @ 3897335033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---