Simulation Results: aes/masked

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.88 %
  • code
  • 93.47 %
  • assert
  • 98.23 %
  • func
  • 74.95 %
  • block
  • 94.05 %
  • line
  • 95.75 %
  • branch
  • 86.80 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 132.922us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 96.771us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 118.105us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 56.019us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 256.853us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 195.249us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 200.495us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 56.019us 1 1 100.00
aes_csr_aliasing 3.000s 195.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 96.771us 1 1 100.00
aes_config_error 3.000s 110.948us 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 96.771us 1 1 100.00
aes_config_error 3.000s 110.948us 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 107.487us 1 1 100.00
aes_b2b 5.000s 496.374us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 96.771us 1 1 100.00
aes_config_error 3.000s 110.948us 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
aes_alert_reset 4.000s 130.855us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 105.548us 1 1 100.00
aes_config_error 3.000s 110.948us 1 1 100.00
aes_alert_reset 4.000s 130.855us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 101.189us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 475.886us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 130.855us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 107.487us 1 1 100.00
aes_sideload 3.000s 157.953us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 105.752us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 14.000s 202.509us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 127.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 298.993us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 298.993us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 118.105us 1 1 100.00
aes_csr_rw 2.000s 56.019us 1 1 100.00
aes_csr_aliasing 3.000s 195.249us 1 1 100.00
aes_same_csr_outstanding 1.000s 146.412us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 118.105us 1 1 100.00
aes_csr_rw 2.000s 56.019us 1 1 100.00
aes_csr_aliasing 3.000s 195.249us 1 1 100.00
aes_same_csr_outstanding 1.000s 146.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 88.347us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 474.361us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1164.531us 1 1 100.00
aes_tl_intg_err 3.000s 623.858us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 623.858us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 130.855us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 96.771us 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
aes_alert_reset 4.000s 130.855us 1 1 100.00
aes_core_fi 3.000s 92.925us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 110.948us 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
aes_core_fi 3.000s 92.925us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 82.040us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 85.941us 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 107.487us 1 1 100.00
aes_sideload 3.000s 157.953us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 85.941us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 85.941us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 85.941us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 85.941us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 85.941us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 107.487us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 535.256us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
aes_ctr_fi 1.000s 56.368us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 535.256us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 535.256us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_ctr_fi 1.000s 56.368us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 535.256us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
aes_ctr_fi 1.000s 56.368us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 130.855us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
aes_ctr_fi 1.000s 56.368us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
aes_ctr_fi 1.000s 56.368us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_ctr_fi 1.000s 56.368us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 535.256us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 535.256us 0 1 0.00
aes_control_fi 2.000s 64.756us 1 1 100.00
aes_cipher_fi 16.000s 10017.822us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 38.000s 6763.481us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 98986700083078251639733127494186063339547743473982930583820990427109100567612 43779
UVM_INFO @ 202509460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 19735634719097607908593355516882259050443672779886879980865708332917731429442 1020
UVM_INFO @ 6763481154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 66821644438885879342879584733988225654179150615903465651252405430953481434803 5850
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 9128896553021598832557130359782226532620195375183034435369176199621349012316 146
UVM_INFO @ 10017822348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---