Simulation Results: aes/unmasked

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.23 %
  • code
  • 89.56 %
  • assert
  • 97.92 %
  • func
  • 74.19 %
  • block
  • 89.40 %
  • line
  • 91.73 %
  • branch
  • 79.65 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 95.263us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 52.230us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 51.568us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 64.021us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 575.198us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 141.013us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 401.887us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 64.021us 1 1 100.00
aes_csr_aliasing 2.000s 141.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 52.230us 1 1 100.00
aes_config_error 2.000s 159.095us 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 52.230us 1 1 100.00
aes_config_error 2.000s 159.095us 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 67.960us 1 1 100.00
aes_b2b 3.000s 602.475us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 52.230us 1 1 100.00
aes_config_error 2.000s 159.095us 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
aes_alert_reset 1.000s 92.616us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 90.934us 1 1 100.00
aes_config_error 2.000s 159.095us 1 1 100.00
aes_alert_reset 1.000s 92.616us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 68.706us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 253.494us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 92.616us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 67.960us 1 1 100.00
aes_sideload 2.000s 78.011us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 130.451us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 10.000s 85.389us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 66.329us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 147.201us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 147.201us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 51.568us 1 1 100.00
aes_csr_rw 1.000s 64.021us 1 1 100.00
aes_csr_aliasing 2.000s 141.013us 1 1 100.00
aes_same_csr_outstanding 1.000s 60.729us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 51.568us 1 1 100.00
aes_csr_rw 1.000s 64.021us 1 1 100.00
aes_csr_aliasing 2.000s 141.013us 1 1 100.00
aes_same_csr_outstanding 1.000s 60.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 115.196us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 594.926us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 418.507us 1 1 100.00
aes_tl_intg_err 2.000s 294.504us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 294.504us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 92.616us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 52.230us 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
aes_alert_reset 1.000s 92.616us 1 1 100.00
aes_core_fi 11.000s 10010.624us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 2.000s 159.095us 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
aes_core_fi 11.000s 10010.624us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 240.733us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 62.773us 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 67.960us 1 1 100.00
aes_sideload 2.000s 78.011us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 62.773us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 62.773us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 62.773us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 62.773us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 62.773us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 67.960us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.626us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
aes_ctr_fi 2.000s 67.916us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.626us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.626us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_ctr_fi 2.000s 67.916us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.626us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
aes_ctr_fi 2.000s 67.916us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 92.616us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
aes_ctr_fi 2.000s 67.916us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
aes_ctr_fi 2.000s 67.916us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_ctr_fi 2.000s 67.916us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 103.626us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 103.626us 0 1 0.00
aes_control_fi 2.000s 63.561us 1 1 100.00
aes_cipher_fi 1.000s 71.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 245.938us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 102126184630361891530361156141462837065804148782793886859883373225867716187805 6364
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 68512410936377326698137189395132164389896149707133935082592293906061392171211 141
UVM_INFO @ 10010623989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 66647011685209982334091101148820018979985673590170419179623796100062885332218 236
UVM_INFO @ 245937702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---