Simulation Results

Simulation Results: chip

25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
74.11 %

code
84.53 %

assert
97.37 %

func
40.44 %

line
94.41 %

branch
94.26 %

cond
89.53 %

toggle
87.30 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		78.34%
V2S		100.00%
V3		65.38%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	153.750s	2900.405us	1	1	100.00
	chip_sw_example_rom	90.550s	2277.741us	1	1	100.00
	chip_sw_example_manufacturer	144.970s	2781.535us	1	1	100.00
	chip_sw_example_concurrency	154.820s	2731.856us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	284.570s	7852.107us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	198.830s	3757.640us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2939.950s	44241.604us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4672.690s	37284.890us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	341.680s	6150.156us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4672.690s	37284.890us	1	1	100.00
	chip_csr_rw	198.830s	3757.640us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	5.390s	47.858us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	340.580s	4609.613us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	340.580s	4609.613us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	340.580s	4609.613us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	360.680s	4678.276us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	360.680s	4678.276us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	353.970s	4456.414us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	372.080s	4136.215us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	362.390s	3774.637us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1727.510s	12879.979us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	976.670s	8356.141us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	614.720s	7948.569us	1	1	100.00

217/277 passed

78.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	170.390s	4896.806us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	170.390s	4896.806us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	175.400s	3491.488us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	133.120s	3514.680us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	203.480s	3940.614us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	90.620s	3057.912us	1	1	100.00
	chip_tap_straps_testunlock0	80.690s	2221.616us	1	1	100.00
	chip_tap_straps_rma	177.430s	4391.954us	1	1	100.00
	chip_tap_straps_prod	95.420s	2756.165us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	423.770s	6462.738us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	423.770s	6462.738us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	709.700s	7757.432us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1191.970s	11422.446us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	359.660s	4060.189us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	664.110s	5959.817us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3950.250s	19505.829us	1	1	100.00
	chip_sw_aes_enc_jitter_en	212.520s	3468.562us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	662.640s	6252.529us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	187.150s	2934.107us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	797.170s	7526.394us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	185.300s	3102.062us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	313.690s	4784.174us	1	1	100.00
	chip_sw_clkmgr_jitter	195.410s	3022.114us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	213.750s	3112.098us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	627.270s	9428.553us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	286.480s	5220.841us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	118.920s	2942.278us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	286.480s	5220.841us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	154.600s	2662.590us	1	1	100.00
	chip_sw_aes_smoketest	190.950s	3771.251us	1	1	100.00
	chip_sw_aon_timer_smoketest	188.370s	3032.618us	1	1	100.00
	chip_sw_clkmgr_smoketest	172.770s	2569.163us	1	1	100.00
	chip_sw_csrng_smoketest	168.350s	3264.233us	1	1	100.00
	chip_sw_entropy_src_smoketest	667.580s	5111.435us	1	1	100.00
	chip_sw_gpio_smoketest	187.690s	3230.656us	1	1	100.00
	chip_sw_hmac_smoketest	222.180s	3270.383us	1	1	100.00
	chip_sw_kmac_smoketest	182.360s	3533.829us	1	1	100.00
	chip_sw_otbn_smoketest	739.760s	6941.057us	1	1	100.00
	chip_sw_pwrmgr_smoketest	389.410s	7160.076us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	256.550s	5056.091us	1	1	100.00
	chip_sw_rv_plic_smoketest	130.000s	2817.090us	1	1	100.00
	chip_sw_rv_timer_smoketest	200.940s	3700.026us	1	1	100.00
	chip_sw_rstmgr_smoketest	152.620s	2353.249us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	136.560s	3053.147us	1	1	100.00
	chip_sw_uart_smoketest	162.730s	2992.191us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	150.820s	2567.474us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	431.860s	6498.200us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7998.190s	64303.718us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3235.900s	15406.252us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	30.825s	0.000us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	400.400s	4241.693us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	214.770s	4337.548us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7511.230s	55995.099us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7678.880s	59332.659us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	52.660s	2786.543us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	52.660s	2786.543us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4672.690s	37284.890us	1	1	100.00
	chip_same_csr_outstanding	2778.700s	26600.828us	1	1	100.00
	chip_csr_hw_reset	284.570s	7852.107us	1	1	100.00
	chip_csr_rw	198.830s	3757.640us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4672.690s	37284.890us	1	1	100.00
	chip_same_csr_outstanding	2778.700s	26600.828us	1	1	100.00
	chip_csr_hw_reset	284.570s	7852.107us	1	1	100.00
	chip_csr_rw	198.830s	3757.640us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	27.300s	525.205us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.650s	50.204us	1	1	100.00
	xbar_smoke_large_delays	49.540s	9117.448us	1	1	100.00
	xbar_smoke_slow_rsp	49.090s	5603.312us	1	1	100.00
	xbar_random_zero_delays	21.860s	343.008us	1	1	100.00
	xbar_random_large_delays	105.280s	18603.140us	1	1	100.00
	xbar_random_slow_rsp	37.820s	4446.123us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	23.760s	308.204us	1	1	100.00
	xbar_error_and_unmapped_addr	18.700s	250.417us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	7.360s	136.859us	1	1	100.00
	xbar_error_and_unmapped_addr	18.700s	250.417us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	52.460s	1955.371us	1	1	100.00
	xbar_access_same_device_slow_rsp	219.090s	28038.583us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	18.980s	342.387us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	59.080s	1115.604us	1	1	100.00
	xbar_stress_all_with_error	131.750s	2808.433us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	61.440s	177.672us	1	1	100.00
	xbar_stress_all_with_reset_error	331.690s	9431.421us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3235.900s	15406.252us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2635.340s	29313.922us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3190.780s	16659.227us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	47.450s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	70.890s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	32.357s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	8.780s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	17.449s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	49.321s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	22.695s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	20.162s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	9.669s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	32.778s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	165.455s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	42.146s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	60.111s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	83.372s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	34.002s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	21.880s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	23.300s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	21.950s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.990s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	23.190s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.000s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	20.440s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	23.390s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.650s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.610s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	23.040s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	21.260s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.740s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.570s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.620s	10.220us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	130.139s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	120.688s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	66.811s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	52.402s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	49.474s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	6095.710s	28613.846us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5975.890s	31132.388us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6115.870s	33320.638us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3249.800s	16451.986us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3339.910s	34627.633us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3339.910s	34627.633us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	223.790s	3493.781us	1	1	100.00
	chip_sw_aes_enc_jitter_en	212.520s	3468.562us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	140.730s	2895.815us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	147.620s	2812.749us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	713.420s	7036.309us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	191.010s	3036.735us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	291.390s	4806.869us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	522.600s	5460.749us	1	1	100.00
	chip_plic_all_irqs_10	316.720s	3581.437us	1	1	100.00
	chip_plic_all_irqs_20	410.510s	4845.169us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	190.310s	3349.314us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1107.160s	11054.422us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	407.040s	5666.463us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	144.020s	2778.881us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.167s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	914.610s	7298.130us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	793.360s	6501.923us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	806.400s	8412.488us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8584.310s	254503.991us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	244.010s	4061.990us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	389.410s	7160.076us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	244.010s	4061.990us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	397.310s	7540.270us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	397.310s	7540.270us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	360.280s	7673.707us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	462.060s	5980.512us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	610.740s	5983.975us	1	1	100.00
	chip_sw_aes_idle	147.620s	2812.749us	1	1	100.00
	chip_sw_hmac_enc_idle	185.960s	3124.103us	1	1	100.00
	chip_sw_kmac_idle	135.980s	2814.225us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	248.190s	4467.578us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	311.370s	4697.143us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	404.130s	5909.240us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	216.650s	4959.555us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	731.570s	10037.707us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	421.570s	4232.552us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	377.650s	5419.470us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	452.520s	4322.045us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	431.610s	5177.643us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	440.260s	4688.029us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	417.150s	5681.545us	1	1	100.00
	chip_sw_ast_clk_outputs	709.700s	7757.432us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	339.700s	6170.378us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	452.520s	4322.045us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	431.610s	5177.643us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	359.660s	4060.189us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	664.110s	5959.817us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3950.250s	19505.829us	1	1	100.00
	chip_sw_aes_enc_jitter_en	212.520s	3468.562us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	662.640s	6252.529us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	187.150s	2934.107us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	797.170s	7526.394us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	185.300s	3102.062us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	313.690s	4784.174us	1	1	100.00
	chip_sw_clkmgr_jitter	195.410s	3022.114us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	126.750s	2235.477us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	413.400s	4525.675us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	684.210s	7164.802us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4377.490s	25122.099us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	142.860s	3424.594us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	164.940s	3015.084us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	604.930s	7239.113us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	200.990s	3620.993us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	397.140s	6265.975us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1059.960s	23759.075us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	13763.130s	159412.424us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	709.700s	7757.432us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	381.490s	4389.531us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	290.070s	3891.170us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	914.610s	7298.130us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2176.340s	24240.282us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	138.380s	2819.688us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	586.990s	7596.740us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	198.800s	2919.097us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2629.880s	15616.760us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	158.460s	3151.168us	1	1	100.00
	chip_sw_edn_entropy_reqs	920.920s	6878.408us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	158.460s	3151.168us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2176.340s	24240.282us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	165.670s	3311.996us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1215.030s	17352.464us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	618.560s	5821.522us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	664.110s	5959.817us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	387.540s	4139.486us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	359.660s	4060.189us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3383.060s	44063.701us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1215.030s	17352.464us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	239.350s	3922.580us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	797.810s	7040.372us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	139.230s	3114.172us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3383.060s	44063.701us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	139.230s	3114.172us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	139.230s	3114.172us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	139.230s	3114.172us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	139.230s	3114.172us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	295.350s	12784.363us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	599.340s	5512.412us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	417.150s	6230.311us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	417.150s	6230.311us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	176.890s	2938.362us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	187.150s	2934.107us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	185.960s	3124.103us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1221.120s	10021.259us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1804.770s	12018.526us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	365.870s	4302.419us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	368.200s	4866.300us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	396.220s	5277.069us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	264.610s	3990.943us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	797.810s	7040.372us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	797.170s	7526.394us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1430.390s	11446.614us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	713.420s	7036.309us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4021.870s	20026.870us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	136.380s	2448.446us	1	1	100.00
	chip_sw_kmac_mode_kmac	196.680s	3148.334us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	185.300s	3102.062us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	797.810s	7040.372us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	143.570s	2600.891us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1053.150s	7670.417us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	135.980s	2814.225us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	291.390s	4806.869us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	90.620s	3057.912us	1	1	100.00
	chip_tap_straps_rma	177.430s	4391.954us	1	1	100.00
	chip_tap_straps_prod	95.420s	2756.165us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	139.950s	3429.281us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1867.990s	13396.511us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	139.230s	3114.172us	0	1	0.00
	chip_sw_flash_rma_unlocked	3383.060s	44063.701us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	206.580s	3629.036us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	522.750s	7314.770us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	566.690s	6266.678us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	564.690s	8304.005us	0	1	0.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
	chip_sw_keymgr_key_derivation	797.810s	7040.372us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	316.270s	9043.661us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	484.360s	8758.394us	1	1	100.00
	chip_prim_tl_access	295.350s	12784.363us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	339.700s	6170.378us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	421.570s	4232.552us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	377.650s	5419.470us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	452.520s	4322.045us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	431.610s	5177.643us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	440.260s	4688.029us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	417.150s	5681.545us	1	1	100.00
	chip_tap_straps_dev	90.620s	3057.912us	1	1	100.00
	chip_tap_straps_rma	177.430s	4391.954us	1	1	100.00
	chip_tap_straps_prod	95.420s	2756.165us	1	1	100.00
	chip_rv_dm_lc_disabled	382.400s	16138.026us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	153.790s	4087.413us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	87.810s	2966.722us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	81.940s	3001.178us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	159.950s	3525.906us	1	1	100.00
chip_lc_test_locked				2	2	100.00
	chip_sw_lc_walkthrough_testunlocks	1640.160s	25496.046us	1	1	100.00
	chip_rv_dm_lc_disabled	382.400s	16138.026us	1	1	100.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	544.230s	8802.107us	0	1	0.00
	chip_sw_lc_walkthrough_prod	650.950s	10978.771us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	682.360s	9163.423us	1	1	100.00
	chip_sw_lc_walkthrough_rma	412.950s	7514.121us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1640.160s	25496.046us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	79.750s	2050.315us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	68.340s	2833.105us	1	1	100.00
	rom_volatile_raw_unlock	98.547s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4048.350s	17585.088us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3950.250s	19505.829us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	610.740s	5983.975us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	610.740s	5983.975us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	610.740s	5983.975us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	304.340s	3386.715us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1215.030s	17352.464us	1	1	100.00
	chip_sw_otbn_mem_scramble	304.340s	3386.715us	1	1	100.00
	chip_sw_keymgr_key_derivation	797.810s	7040.372us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	410.440s	4480.881us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	164.610s	3597.863us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1215.030s	17352.464us	1	1	100.00
	chip_sw_otbn_mem_scramble	304.340s	3386.715us	1	1	100.00
	chip_sw_keymgr_key_derivation	797.810s	7040.372us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	410.440s	4480.881us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	164.610s	3597.863us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	353.750s	4966.195us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	139.950s	3429.281us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	206.580s	3629.036us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	522.750s	7314.770us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	566.690s	6266.678us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	564.690s	8304.005us	0	1	0.00
	chip_sw_lc_ctrl_transition	609.230s	9364.491us	1	1	100.00
	chip_prim_tl_access	295.350s	12784.363us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	295.350s	12784.363us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	871.990s	7374.591us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	65.970s	3162.166us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1184.030s	26959.346us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	263.300s	7364.984us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	469.120s	7951.265us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	399.190s	7468.039us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1159.830s	26791.104us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	234.850s	6136.700us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	397.310s	7540.270us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	887.450s	10751.972us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	384.060s	5301.221us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	65.970s	3162.166us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	257.170s	4610.239us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	429.830s	8349.790us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	315.160s	7513.644us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	175.090s	2874.642us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	556.680s	13383.262us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	754.950s	7932.253us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1050.630s	12972.101us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1476.460s	27455.396us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	167.560s	2715.025us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	316.270s	9043.661us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	316.270s	9043.661us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1050.630s	12972.101us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	556.680s	13383.262us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	384.060s	5301.221us	1	1	100.00
	chip_sw_pwrmgr_smoketest	389.410s	7160.076us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	256.810s	4597.771us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	478.310s	6270.240us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	347.940s	5464.235us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1107.160s	11054.422us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	184.880s	3508.022us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	793.360s	6501.923us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	469.130s	5326.756us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	474.370s	5406.661us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	204.060s	2921.859us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	164.610s	3597.863us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	478.310s	6270.240us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	478.310s	6270.240us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	134.210s	2570.973us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1164.530s	15616.360us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1053.110s	13867.419us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	256.810s	4597.771us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	172.780s	3105.802us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	337.890s	6760.516us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	177.430s	4391.954us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	382.400s	16138.026us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	522.600s	5460.749us	1	1	100.00
	chip_plic_all_irqs_10	316.720s	3581.437us	1	1	100.00
	chip_plic_all_irqs_20	410.510s	4845.169us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	157.340s	3380.912us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	166.000s	2734.708us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3235.900s	15406.252us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	211.490s	3401.498us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	185.720s	3293.677us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	254.030s	3525.104us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	183.860s	3077.427us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	410.440s	4480.881us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	313.690s	4784.174us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	381.880s	6863.645us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	424.860s	6967.832us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	484.360s	8758.394us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
	chip_sw_data_integrity_escalation	423.770s	6462.738us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	754.950s	7932.253us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1119.520s	23935.226us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	134.330s	2784.224us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	207.340s	3367.023us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	320.360s	4027.082us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1119.520s	23935.226us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1119.520s	23935.226us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2402.690s	20751.017us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2402.690s	20751.017us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	270.430s	6287.321us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3339.910s	34627.633us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	162.360s	2784.642us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	204.430s	3727.665us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	304.600s	3491.166us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	350.260s	4026.634us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1001.370s	8656.737us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5633.890s	31396.793us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1840.420s	12353.649us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	178.070s	2659.826us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	193.480s	2849.607us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	109.040s	2977.794us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10277.240s	71152.480us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1196.870s	6697.034us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	500.260s	7952.393us	0	1	0.00
	rom_e2e_jtag_debug_dev	177.200s	3432.886us	0	1	0.00
	rom_e2e_jtag_debug_rma	455.860s	7224.675us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	66.300s	2226.334us	0	1	0.00
	rom_e2e_jtag_inject_dev	70.660s	2739.027us	0	1	0.00
	rom_e2e_jtag_inject_rma	250.610s	4944.365us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	36.421s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	288.300s	4268.029us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	357.030s	3060.147us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	829.070s	5738.519us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	711.200s	5335.931us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	238.400s	2443.527us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	614.080s	5218.202us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	53.350s	2066.896us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	176.400s	3492.175us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	204.810s	5074.203us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	316.760s	4542.639us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1050.630s	12972.101us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	500.260s	7952.393us	0	1	0.00
	rom_e2e_jtag_debug_dev	177.200s	3432.886us	0	1	0.00
	rom_e2e_jtag_debug_rma	455.860s	7224.675us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	351.730s	5185.718us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	463.690s	6296.942us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5668.760s	38820.329us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5668.760s	38820.329us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	200.010s	3716.400us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	360.680s	4678.276us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2953.800s	18747.091us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	184.060s	2675.457us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	19.210s	10.160us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	6.390s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	184.630s	3661.218us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	232.800s	3796.959us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	251.430s	4457.825us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	7.932s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	228.160s	3840.879us	1	1	100.00
	ate_bootstrap_flash_erase	644.690s	10010.120us	0	1	0.00
	ate_bootstrap_one_frame	6461.160s	45925.942us	1	1	100.00
	ate_bootstrap_disjoint	9632.590s	84792.315us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	38050998971294572441891440113635861722732833847973091179168681134416684149919	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	28930725422806177635364307531405298538122065212131719154483387786951568214276	None	Another command (pid=372438) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=442092) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=380620) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	34809031078948773515677467654812766059115017127246156096749046415581033608621	None	Another command (pid=721138) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=581235) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=701581) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	16089868868912090892435907001301526093246412260748438550329073286558002424840	None	Another command (pid=630546) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=522465) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=580748) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40833931112412053949837407623693867091049819712554963512536621086578191839693	None	Another command (pid=580234) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=580041) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=572647) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	71549875846526298539947705261543901593618201779672839745622084568815101469595	None	Another command (pid=572647) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=585688) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=479674) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	81277394987734551534930299215649335455702815352610749903261947071595842082016	None	Another command (pid=380620) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=446362) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=420637) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	87442107877007864688200174510735743305947740945515701502776126924793993035954	None	Another command (pid=424801) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=479621) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=461818) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	77025911276216006761403129055011610292336975198883638854144404474962847759802	None	Another command (pid=571403) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=567131) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=569171) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26803037681457576790523813891312115424696723335727720035896311109820212116802	None	Another command (pid=569171) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=435212) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=572030) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	27161632406099684321446942490354117875009501193050493541800548180350895887489	None	Another command (pid=624548) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=630546) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=522465) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	21046718506151249287557448981217914872673854940152392842511742876536876359632	None	Another command (pid=618688) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=563859) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=634613) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	38934604018636276051846873649089867335621887412941868448253018761820431528426	None	---- STDERR ---- Another command (pid=460380) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=427678) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	68737894906967401039442912774117510988635635000994051981217550200651309560031	None	---- STDERR ---- Another command (pid=603215) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	43811581644049653349218048087627921781533275130732541132158253834362626077275	None	Another command (pid=651310) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=570438) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=618688) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	14691958529470157923945931705366722520163450107972401384290629521868532534385	None	Another command (pid=567131) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=569171) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=435212) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	46383080505865936592491186188887170674271692653585444185797054538922142180520	None	Another command (pid=580234) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=580041) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=572647) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	54435978684895585190857151213263354473930626459450494963555000253346520279643	None	Another command (pid=657379) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=682330) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=669334) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	40313677912366217200243466460404770668842272060390648744059335694720661276047	None	Another command (pid=461818) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=389530) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=516354) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	40059007503996372307482350424850912052994270433589889871195341800213629236471	None	Another command (pid=516354) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=460380) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=440586) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	36711927037171577519431659753760155912734339922107120409712382496176434355573	None	Another command (pid=424801) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=461818) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=389530) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	38331637298618965672081692785197761746581242767104094099844001667359684379366	None	Another command (pid=389530) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=539135) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=460380) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	5018372941325266947298030067331629119152712002312016952177140700210906128123	None	Another command (pid=442092) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=380620) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=404836) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	111045373161302324783827445093857503279208984407684473009667131452556145034509	None	Another command (pid=442092) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=380620) is running. Waiting for it to complete on the server (server_pid=266846)... Another command (pid=446362) is running. Waiting for it to complete on the server (server_pid=266846)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	53078968914678092107156797985502487842862585341323746424559552501638320340553	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	30514817145419095669861014807557642153693717355803506039303930640708256721642	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	64669705377992635735473043467814050345767268480658934368753960453246172625504	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	96202996990648318566787418083625253411617992346574980269082728111222719908608	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	11457807714984055288496158477172381055239425525846077521048845021663437732847	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	36590146217083338144669541012877467710512366429724462446451415023261774523564	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	100213590746530278698220387448353701155647194390470141389313533614603968706616	310	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	14558756588229848340991258142857445050138053064052902832846247614261013364462	365	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17463825490780041492424993961245620611827722902816707549651146101364319391719	366	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	54515017224807906856736569999471205630210011203448742497740497367510954874229	363	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	92597542812512803363328893024157255027463711589175511004289030347011657185152	328	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	71757195550491573725659031052342394336142534400103944313783307251930420271507	325	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	59595493683037859785529956713767583536625429283494277963313486378721072472601	325	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				4 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	23037529431302954599413536855868305518336935015599665186224990321882908081630	344	UVM_ERROR @ 13383.262000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 13383.262000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	37560406226928425702113245834832891675545035052778884263545065756679333151074	314	UVM_ERROR @ 6136.700000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6136.700000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15800251413816378565707077545980416623573245294285900237961680844477333180513	330	UVM_ERROR @ 8349.790000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8349.790000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	87387940490672152898466726192269195324519653748969947395354587187362710604985	319	UVM_ERROR @ 7540.270000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7540.270000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	80916525085397064256088488936261584839030116357883881224644228928421049638876	369	UVM_INFO @ 8802.106741 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	59668969014348189935768690886511108321351590086447364924060248320979577140894	369	UVM_INFO @ 10978.770838 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	81455516152566269124251001487683820292294549560928204903789872360814878250701	341	UVM_INFO @ 7514.120954 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	15181742332263502496763058140998407800779375949802082113207160018761717768728	328	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	36673740425262050920024512420327833186058529892248343327806750365368575437519	328	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	96903794147017037408126600558003482172757589287416530926215787551149807699940	325	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	40703721268409242337239855126180982859799506998864068485201881846746100850291	316	UVM_ERROR @ 3492.175176 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3492.175176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	69116801667937481942843734056536290220330714843669766373489351515214483356889	312	UVM_ERROR @ 2819.688008 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2819.688008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	76455507001241769409908798618141868887014093625103239182031173832950240325655	353	UVM_INFO @ 12018.525649 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	45773905031855116468170797088998666253795066464450322133829633409106328676594	334	UVM_INFO @ 20026.869736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	83915178783632775682402882113559937284937579353562071476451041469965979634663	362	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	55023903475077885546861029120289644728089197258505380092014117196305111066624	325	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	9541623836746190322459290361748733038007175644026621435950942956443994745576	369	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	60353160499453573611820519471531046622779422658697650977786218998799505143220	328	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	92019532344052501660115932344277739976230986377718641561472606383813995458204	301	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	76320109636887192833269671146603202023967355724275441130902529406015941504612	329	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	111322277909564988026146760201362963139715261556081376671439819609613513230905	309	UVM_INFO @ 3114.171997 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	36877628170745733587938438417279149454628942703127032614598740837595151737751	342	UVM_INFO @ 8304.004683 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	96370785715295010687578856832798462247031122146348985090097347661752165813931	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	909314782236983396627514189330478609290700488862221034702535648108600055057	303	UVM_ERROR @ 3162.166399 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 3162.166399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	8330801458291122385640220918912966753381939095368440409381410715051288762072	313	UVM_ERROR @ 2874.641848 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2874.641848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	74800968481924603993543495436016116914243872180080101369881169551864300548062	332	UVM_INFO @ 34627.632937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:297)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	114516839761159872213922540268141645463724964355409041458466069654433766386660	307	UVM_INFO @ 3036.735020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	65496938195965220885216856111522322591059418987343571224746398915927401411448	308	UVM_INFO @ 2778.880780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	58318301783909644522529292674849006643301825529494388119964910935354086262872	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	23737187854597936641142363818174854018240532186733613228804374858693066276281	217	TL item was: req: (cip_tl_seq_item@33888) { a_addr: 'h10708 a_data: 'h3871b924 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h18d54 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2786.542724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	51259486734522815920368561225647430903857819930599948414340658315788232580022	343	UVM_INFO @ 4268.028702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	106189835027307739405239479793425489653872970813971315607250080396659155118193	327	UVM_INFO @ 11422.445754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	31554398250314754307410567715744492400669052504643927275629042881725382712699	272	UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	45354097519996159182152747462431957771938289809956873738629335767666840485294	325	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	13222221556191258562280419295166922498540418629156410579623966626362714894721	327	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	99652324435567743014504337013815420874539314401398025801287308721040250863214	327	UVM_ERROR @ 6498.200278 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 6498.200278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---