Simulation Results: clkmgr

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.87 %
  • code
  • 98.22 %
  • assert
  • 95.48 %
  • func
  • 84.91 %
  • line
  • 99.00 %
  • branch
  • 98.64 %
  • cond
  • 94.27 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 26.940us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.760s 20.219us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.190s 784.466us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.040s 86.352us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.810s 29.928us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
clkmgr_csr_aliasing 1.040s 86.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.880s 16.617us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.930s 45.267us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.830s 28.977us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.730s 41.633us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 26.940us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.400s 1643.820us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.700s 916.018us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.400s 1643.820us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 25.520s 13149.330us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.790s 60.456us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.230s 26.542us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.230s 26.542us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 20.219us 1 1 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
clkmgr_csr_aliasing 1.040s 86.352us 1 1 100.00
clkmgr_same_csr_outstanding 0.900s 22.298us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 20.219us 1 1 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
clkmgr_csr_aliasing 1.040s 86.352us 1 1 100.00
clkmgr_same_csr_outstanding 0.900s 22.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.170s 124.122us 0 1 0.00
clkmgr_tl_intg_err 1.960s 147.951us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.130s 96.006us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.130s 96.006us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.130s 96.006us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.130s 96.006us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 6.570s 2088.951us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.960s 147.951us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.400s 1643.820us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.700s 916.018us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.130s 96.006us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.680s 24.894us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.730s 24.644us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.950s 102.180us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.760s 21.295us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.700s 35.858us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.170s 124.122us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 23.079us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.170s 124.122us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.490s 1115.701us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 10.820s 1212.315us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 17929113597579083287944416628342027478801582853173353332684058927609966627903 75
UVM_INFO @ 2088951303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 70414683825497685706428422218421588911796266248276347896685696120433104141259 100
UVM_INFO @ 124121752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---