Simulation Results: csrng

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.62 %
  • code
  • 92.35 %
  • assert
  • 94.32 %
  • func
  • 76.20 %
  • block
  • 97.05 %
  • line
  • 97.76 %
  • branch
  • 92.68 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 67.374us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 39.377us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 14.820us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 15.000s 1017.558us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 65.912us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 117.275us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 14.820us 1 1 100.00
csrng_csr_aliasing 2.000s 65.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
alerts 1 1 100.00
csrng_alert 4.000s 81.484us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 160.847us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 160.847us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 224.000s 15392.586us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 29.084us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 40.318us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 27.922us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 27.922us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 39.377us 1 1 100.00
csrng_csr_rw 2.000s 14.820us 1 1 100.00
csrng_csr_aliasing 2.000s 65.912us 1 1 100.00
csrng_same_csr_outstanding 4.000s 159.371us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 39.377us 1 1 100.00
csrng_csr_rw 2.000s 14.820us 1 1 100.00
csrng_csr_aliasing 2.000s 65.912us 1 1 100.00
csrng_same_csr_outstanding 4.000s 159.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
csrng_tl_intg_err 4.000s 285.196us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 1.000s 45.149us 1 1 100.00
csrng_csr_rw 2.000s 14.820us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 4.000s 81.484us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 224.000s 15392.586us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 4.000s 81.484us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 224.000s 15392.586us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 4.000s 81.484us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 285.196us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
csrng_sec_cm 3.000s 93.694us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 165.121us 1 1 100.00
csrng_err 2.000s 25.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 31.000s 828.491us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 56412414166395867079364195779389629357545726542358770347111793699256505029952 110
UVM_INFO @ 160846901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 99460866978738595280036506754966827518639929370933242611091693093370146592618 151
UVM_INFO @ 828491278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---