Simulation Results: edn/edn0

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.05 %
  • code
  • 79.18 %
  • assert
  • 95.01 %
  • func
  • 80.95 %
  • line
  • 97.12 %
  • branch
  • 89.96 %
  • cond
  • 85.61 %
  • toggle
  • 75.88 %
  • FSM
  • 47.31 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 17.107us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.800s 52.550us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 124.359us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.670s 128.146us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 62.674us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.140s 41.841us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 124.359us 1 1 100.00
edn_csr_aliasing 1.080s 62.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.590s 53.487us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.590s 53.487us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.590s 53.487us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.750s 39.585us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 70.095us 1 1 100.00
errs 1 1 100.00
edn_err 1.050s 54.766us 1 1 100.00
disable 1 2 50.00
edn_disable 0.800s 12.487us 1 1 100.00
edn_disable_auto_req_mode 1.100s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.050s 848.555us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 44.765us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 145.685us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.770s 37.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.770s 37.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.800s 52.550us 1 1 100.00
edn_csr_rw 0.810s 124.359us 1 1 100.00
edn_csr_aliasing 1.080s 62.674us 1 1 100.00
edn_same_csr_outstanding 1.000s 51.662us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.800s 52.550us 1 1 100.00
edn_csr_rw 0.810s 124.359us 1 1 100.00
edn_csr_aliasing 1.080s 62.674us 1 1 100.00
edn_same_csr_outstanding 1.000s 51.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.730s 405.762us 1 1 100.00
edn_tl_intg_err 1.970s 94.794us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 19.546us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 70.095us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.730s 405.762us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.730s 405.762us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.730s 405.762us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.730s 405.762us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 70.095us 1 1 100.00
edn_sec_cm 4.730s 405.762us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 70.095us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.970s 94.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 74.180s 9940.613us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 48545393377915775164373074869886740598369015135170697047386504924102115732651 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---