Simulation Results: edn/edn1

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.73 %
  • code
  • 82.57 %
  • assert
  • 98.70 %
  • func
  • 81.93 %
  • line
  • 97.95 %
  • branch
  • 92.86 %
  • cond
  • 91.08 %
  • toggle
  • 87.80 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.750s 98.802us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 27.998us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 43.199us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.620s 91.348us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 49.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.150s 506.640us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 43.199us 1 1 100.00
edn_csr_aliasing 0.970s 49.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.350s 54.595us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.350s 54.595us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.350s 54.595us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 23.612us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.890s 88.748us 1 1 100.00
errs 1 1 100.00
edn_err 0.940s 58.669us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 23.954us 1 1 100.00
edn_disable_auto_req_mode 1.140s 52.071us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.440s 315.575us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.680s 39.132us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 54.685us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.050s 171.590us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.050s 171.590us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 27.998us 1 1 100.00
edn_csr_rw 0.740s 43.199us 1 1 100.00
edn_csr_aliasing 0.970s 49.756us 1 1 100.00
edn_same_csr_outstanding 0.900s 45.587us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 27.998us 1 1 100.00
edn_csr_rw 0.740s 43.199us 1 1 100.00
edn_csr_aliasing 0.970s 49.756us 1 1 100.00
edn_same_csr_outstanding 0.900s 45.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.160s 691.079us 1 1 100.00
edn_tl_intg_err 1.640s 267.394us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 18.470us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.890s 88.748us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.160s 691.079us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.160s 691.079us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.160s 691.079us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.160s 691.079us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.890s 88.748us 1 1 100.00
edn_sec_cm 2.160s 691.079us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.890s 88.748us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.640s 267.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 82.180s 12768.236us 1 1 100.00