Simulation Results: entropy_src/rng_4bits

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.72 %
  • code
  • 88.16 %
  • assert
  • 84.07 %
  • func
  • 54.94 %
  • block
  • 94.45 %
  • line
  • 97.11 %
  • branch
  • 86.64 %
  • toggle
  • 76.18 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 30.660us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 158.208us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 130.178us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 490.797us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 118.781us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 19.774us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 130.178us 1 1 100.00
entropy_src_csr_aliasing 3.000s 118.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 30.660us 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
entropy_src_fw_ov 105.000s 13065.918us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 105.000s 13065.918us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 347.000s 14019.516us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
entropy_src_intr 2.000s 109.219us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
entropy_src_functional_alerts 4.000s 185.909us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 226.000s 14167.699us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 1.000s 109.040us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 1.000s 193.259us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 18.177us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 115.658us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 173.576us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 173.576us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 158.208us 1 1 100.00
entropy_src_csr_rw 1.000s 130.178us 1 1 100.00
entropy_src_csr_aliasing 3.000s 118.781us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 108.511us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 158.208us 1 1 100.00
entropy_src_csr_rw 1.000s 130.178us 1 1 100.00
entropy_src_csr_aliasing 3.000s 118.781us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 108.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 62.865us 1 1 100.00
entropy_src_tl_intg_err 2.000s 104.475us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
entropy_src_cfg_regwen 2.000s 95.469us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
entropy_src_fw_ov 105.000s 13065.918us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 1.000s 109.040us 1 1 100.00
entropy_src_sec_cm 2.000s 62.865us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 1.000s 109.040us 1 1 100.00
entropy_src_sec_cm 2.000s 62.865us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 85.000s 13032.566us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 1.000s 109.040us 1 1 100.00
entropy_src_sec_cm 2.000s 62.865us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 1.000s 109.040us 1 1 100.00
entropy_src_sec_cm 2.000s 62.865us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 1.000s 109.040us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 185.909us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 104.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 190.000s 13078.135us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 14.000s 739.828us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 79514123775326521987981356883476666076368983735117324158779836535793021117621 135
UVM_INFO @ 739828330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror repcnts_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 76264398405426440058854605619741711379891696873764991184936328111093131277218 113
UVM_INFO @ 19773597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---