Simulation Results: flash_ctrl

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 94.10 %
  • assert
  • 97.02 %
  • func
  • 95.76 %
  • line
  • 95.96 %
  • branch
  • 97.08 %
  • cond
  • 93.48 %
  • toggle
  • 97.59 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 46.160s 30.274us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.350s 17.665us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.580s 58.021us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 30.140s 1850.098us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 36.270s 1438.704us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.670s 30.416us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
flash_ctrl_csr_aliasing 36.270s 1438.704us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.230s 54.954us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.110s 21.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.390s 43.733us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 27.840s 114.887us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1125.220s 513055.417us 1 1 100.00
flash_ctrl_hw_rma_reset 521.030s 40126.849us 1 1 100.00
flash_ctrl_lcmgr_intg 7.270s 43.544us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1331.790s 248346.734us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 198.990s 13546.310us 1 1 100.00
program_reset 0 1 0.00
flash_ctrl_prog_reset 3603.484s 0.000us 0 1 0.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2446.150s 112704.866us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 63.770s 1264.448us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 17.520s 48.422us 1 1 100.00
flash_ctrl_rw_evict_all_en 17.230s 48.214us 1 1 100.00
flash_ctrl_re_evict 19.010s 155.090us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 157.920s 3045.108us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 157.920s 3045.108us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 303.590s 9071.215us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.840s 160.400us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 425.620s 3159.028us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 364.240s 6722.508us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 331.460s 3748.663us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 877.740s 1322.103us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 11.280s 30.773us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 118.610s 2476.119us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.210s 32.758us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.570s 28.293us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 758.980s 965.796us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 127.290s 3251.187us 1 1 100.00
flash_ctrl_otp_reset 70.330s 76.978us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1125.220s 513055.417us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 97.870s 1501.916us 1 1 100.00
flash_ctrl_intr_wr 59.040s 3395.650us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 95.340s 11039.518us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 176.560s 89681.685us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 48.300s 35215.924us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 40.150s 2717.646us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.090s 31.737us 1 1 100.00
flash_ctrl_ro_derr 120.720s 1697.880us 1 1 100.00
flash_ctrl_rw_derr 130.130s 6351.396us 1 1 100.00
flash_ctrl_derr_detect 100.310s 1065.226us 1 1 100.00
flash_ctrl_integrity 313.910s 8679.263us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.050s 110.289us 1 1 100.00
flash_ctrl_ro_serr 106.770s 1683.477us 1 1 100.00
flash_ctrl_rw_serr 157.160s 8177.052us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 43.090s 757.313us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 47.500s 7861.424us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 95.870s 9418.287us 1 1 100.00
flash_ctrl_write_word_sweep 9.190s 84.009us 1 1 100.00
flash_ctrl_read_word_sweep 7.080s 30.775us 1 1 100.00
flash_ctrl_ro 93.510s 4321.779us 1 1 100.00
flash_ctrl_rw 419.120s 7457.024us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 26.230s 407.583us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 566.010s 81128.019us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 94.450s 10037.484us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.470s 71.927us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 9.140s 65.203us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.680s 49.422us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.680s 49.422us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.580s 58.021us 1 1 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
flash_ctrl_csr_aliasing 36.270s 1438.704us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.110s 398.262us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.580s 58.021us 1 1 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
flash_ctrl_csr_aliasing 36.270s 1438.704us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.110s 398.262us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 22.570s 167.218us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
flash_ctrl_tl_intg_err 419.600s 843.163us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 419.600s 843.163us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 419.600s 843.163us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 18.400s 160.671us 1 1 100.00
flash_ctrl_wr_intg 9.040s 135.668us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 46.160s 30.274us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 70.330s 76.978us 1 1 100.00
flash_ctrl_disable 10.210s 32.758us 1 1 100.00
flash_ctrl_sec_info_access 43.630s 2233.346us 1 1 100.00
flash_ctrl_connect 7.570s 28.293us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 10.070s 229.007us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 11.160s 42.765us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.300s 20.697us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.210s 32.758us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 18.400s 160.671us 1 1 100.00
flash_ctrl_access_after_disable 6.240s 65.341us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 25.030s 28.054us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.210s 32.758us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.840s 160.400us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 419.120s 7457.024us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 157.160s 8177.052us 1 1 100.00
flash_ctrl_rw_derr 130.130s 6351.396us 1 1 100.00
flash_ctrl_integrity 313.910s 8679.263us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1125.220s 513055.417us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.880s 762.873us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.430s 75.526us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.750s 23.597us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1766.020s 1427.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.420s 188.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 170.350s 2120.400us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_prog_reset 76977700961938206894639847408734933413418469214416254790381941581870843348431 None