Simulation Results: hmac

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.55 %
  • code
  • 97.09 %
  • assert
  • 97.60 %
  • func
  • 40.96 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.79 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.270s 428.904us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.820s 27.740us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.870s 104.909us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.680s 7083.958us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.670s 738.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 343.530s 55249.323us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.870s 104.909us 1 1 100.00
hmac_csr_aliasing 4.670s 738.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 48.550s 19582.248us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 71.360s 2251.672us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.460s 956.251us 1 1 100.00
hmac_test_sha384_vectors 424.520s 70230.071us 1 1 100.00
hmac_test_sha512_vectors 20.370s 1302.625us 1 1 100.00
hmac_test_hmac256_vectors 10.090s 800.004us 1 1 100.00
hmac_test_hmac384_vectors 8.070s 3624.802us 1 1 100.00
hmac_test_hmac512_vectors 12.500s 816.788us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 0.850s 58.561us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 25.870s 1441.380us 1 1 100.00
error 1 1 100.00
hmac_error 9.870s 879.147us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 8.770s 343.463us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.270s 428.904us 1 1 100.00
hmac_long_msg 48.550s 19582.248us 1 1 100.00
hmac_back_pressure 71.360s 2251.672us 1 1 100.00
hmac_datapath_stress 25.870s 1441.380us 1 1 100.00
hmac_burst_wr 0.850s 58.561us 1 1 100.00
hmac_stress_all 27.250s 947.360us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.270s 428.904us 1 1 100.00
hmac_long_msg 48.550s 19582.248us 1 1 100.00
hmac_back_pressure 71.360s 2251.672us 1 1 100.00
hmac_datapath_stress 25.870s 1441.380us 1 1 100.00
hmac_wipe_secret 8.770s 343.463us 1 1 100.00
hmac_test_sha256_vectors 9.460s 956.251us 1 1 100.00
hmac_test_sha384_vectors 424.520s 70230.071us 1 1 100.00
hmac_test_sha512_vectors 20.370s 1302.625us 1 1 100.00
hmac_test_hmac256_vectors 10.090s 800.004us 1 1 100.00
hmac_test_hmac384_vectors 8.070s 3624.802us 1 1 100.00
hmac_test_hmac512_vectors 12.500s 816.788us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.270s 428.904us 1 1 100.00
hmac_long_msg 48.550s 19582.248us 1 1 100.00
hmac_back_pressure 71.360s 2251.672us 1 1 100.00
hmac_datapath_stress 25.870s 1441.380us 1 1 100.00
hmac_burst_wr 0.850s 58.561us 1 1 100.00
hmac_error 9.870s 879.147us 1 1 100.00
hmac_wipe_secret 8.770s 343.463us 1 1 100.00
hmac_test_sha256_vectors 9.460s 956.251us 1 1 100.00
hmac_test_sha384_vectors 424.520s 70230.071us 1 1 100.00
hmac_test_sha512_vectors 20.370s 1302.625us 1 1 100.00
hmac_test_hmac256_vectors 10.090s 800.004us 1 1 100.00
hmac_test_hmac384_vectors 8.070s 3624.802us 1 1 100.00
hmac_test_hmac512_vectors 12.500s 816.788us 1 1 100.00
hmac_stress_all 27.250s 947.360us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 27.250s 947.360us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 13.676us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.670s 54.655us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.540s 123.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.540s 123.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.820s 27.740us 1 1 100.00
hmac_csr_rw 0.870s 104.909us 1 1 100.00
hmac_csr_aliasing 4.670s 738.159us 1 1 100.00
hmac_same_csr_outstanding 1.110s 23.069us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.820s 27.740us 1 1 100.00
hmac_csr_rw 0.870s 104.909us 1 1 100.00
hmac_csr_aliasing 4.670s 738.159us 1 1 100.00
hmac_same_csr_outstanding 1.110s 23.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.110s 332.436us 1 1 100.00
hmac_tl_intg_err 3.090s 688.568us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.090s 688.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.270s 428.904us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.720s 88.354us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 74.270s 21472.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.340s 240.098us 1 1 100.00