Simulation Results

Simulation Results: i2c

25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.40 %

code
78.09 %

assert
97.04 %

func
81.08 %

line
96.41 %

branch
92.33 %

cond
84.70 %

toggle
72.95 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	12.510s	5413.349us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.520s	3014.930us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.720s	75.411us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.770s	20.725us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.190s	1117.559us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.530s	218.742us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.860s	37.985us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.770s	20.725us	1	1	100.00
	i2c_csr_aliasing	1.530s	218.742us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.230s	163.804us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	216.650s	8719.784us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	105.490s	5044.948us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.810s	21.078us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	55.200s	7735.278us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	48.660s	5662.912us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.360s	634.713us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.000s	544.475us	1	1	100.00
	i2c_host_fifo_reset_rx	4.210s	889.071us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	37.060s	13304.464us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	24.480s	3132.048us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.660s	59.872us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.250s	502.192us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	16.970s	18954.238us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.640s	751.134us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	10.300s	1080.155us	1	1	100.00
	i2c_target_intr_smoke	5.490s	6348.579us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.000s	250.379us	1	1	100.00
	i2c_target_fifo_reset_tx	1.320s	638.681us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	89.590s	62910.118us	1	1	100.00
	i2c_target_stress_rd	10.300s	1080.155us	1	1	100.00
	i2c_target_intr_stress_wr	1.920s	2454.407us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.250s	11244.200us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.460s	1336.706us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.180s	3947.033us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.410s	411.917us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.320s	828.302us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.110s	628.280us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	105.490s	5044.948us	1	1	100.00
	i2c_host_perf_precise	140.980s	24307.590us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	24.480s	3132.048us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.710s	167.506us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.980s	8276.312us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.820s	570.405us	1	1	100.00
	i2c_target_nack_txstretch	1.560s	270.962us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.220s	701.795us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.820s	954.194us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.910s	44.894us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.730s	19.427us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.360s	51.507us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.360s	51.507us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	75.411us	1	1	100.00
	i2c_csr_rw	0.770s	20.725us	1	1	100.00
	i2c_csr_aliasing	1.530s	218.742us	1	1	100.00
	i2c_same_csr_outstanding	0.880s	37.536us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	75.411us	1	1	100.00
	i2c_csr_rw	0.770s	20.725us	1	1	100.00
	i2c_csr_aliasing	1.530s	218.742us	1	1	100.00
	i2c_same_csr_outstanding	0.880s	37.536us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.030s	148.236us	1	1	100.00
	i2c_sec_cm	1.190s	269.019us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.030s	148.236us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.450s	732.635us	1
target_error_intr				1
	i2c_target_unexp_stop	1.310s	578.183us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	9.760s	3997.418us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				4 test runs
	i2c_host_error_intr	87611532057962889937461725878303202459647936527785778422373959342289456216890	88	UVM_INFO @ 163803627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	10902375519245584410046981612603856733019206257255815913403085730562862830506	123	UVM_INFO @ 8719783607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	55089775730720441585468992582743326332730651396065750645175977788549322814027	95	UVM_INFO @ 3997418366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	85413186143874763273611317401391039278359227878709121406657290582212664730103	81	UVM_INFO @ 59872278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	23721198190969226176492873963172576181790368117857336325557103275828289216651	84	UVM_INFO @ 502192245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	111091200037795225115053094883796083179546293943045689086838039647846228204789	78	UVM_INFO @ 578182718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	89022885610106308142573599496689973380119227672197600673821757863088412838649	96	UVM_INFO @ 732635030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---