Simulation Results: keymgr

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.11 %
  • code
  • 94.82 %
  • assert
  • 97.49 %
  • func
  • 60.02 %
  • line
  • 98.72 %
  • branch
  • 97.63 %
  • cond
  • 93.24 %
  • toggle
  • 96.13 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 12.930s 1592.316us 1 1 100.00
random 1 1 100.00
keymgr_random 4.070s 120.810us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.170s 21.395us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 8.440s 7584.202us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 8.350s 440.609us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.570s 178.622us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
keymgr_csr_aliasing 8.350s 440.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.480s 167.118us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.530s 278.678us 1 1 100.00
keymgr_sideload_kmac 14.060s 811.679us 1 1 100.00
keymgr_sideload_aes 20.820s 9479.305us 1 1 100.00
keymgr_sideload_otbn 4.480s 248.049us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 6.930s 389.513us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.600s 60.921us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.360s 288.506us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.010s 220.189us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 47.930s 2352.700us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 5.230s 1604.416us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 7.360s 764.757us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 1.090s 60.272us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.000s 38.141us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.210s 64.856us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.210s 64.856us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.170s 21.395us 1 1 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
keymgr_csr_aliasing 8.350s 440.609us 1 1 100.00
keymgr_same_csr_outstanding 1.800s 70.954us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.170s 21.395us 1 1 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
keymgr_csr_aliasing 8.350s 440.609us 1 1 100.00
keymgr_same_csr_outstanding 1.800s 70.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
keymgr_tl_intg_err 7.580s 521.574us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 3.110s 208.805us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 3.110s 208.805us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 3.110s 208.805us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 3.110s 208.805us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.230s 477.331us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.580s 521.574us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 3.110s 208.805us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.480s 167.118us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.070s 120.810us 1 1 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.070s 120.810us 1 1 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.070s 120.810us 1 1 100.00
keymgr_csr_rw 1.150s 11.258us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.600s 60.921us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 47.930s 2352.700us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 47.930s 2352.700us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.070s 120.810us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.020s 118.454us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.390s 97.238us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.600s 60.921us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.390s 97.238us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.390s 97.238us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.390s 97.238us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.000s 348.567us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.390s 97.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 8.410s 555.322us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 89028410988557410132812688948013411181268276560770387415325035370288227438301 689
UVM_INFO @ 555322116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---