Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.32 %
  • code
  • 83.95 %
  • assert
  • 94.13 %
  • func
  • 92.88 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.36 %
  • toggle
  • 86.85 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.860s 37.375us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.390s 14.090us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.980s 53.726us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.640s 47.335us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 226.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.860s 122.583us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.980s 53.726us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 226.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.630s 332.180us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.800s 269.021us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.860s 13.983us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.840s 84.314us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.290s 931.808us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_prog_failure 2.840s 84.314us 1 1 100.00
lc_ctrl_errors 6.290s 931.808us 1 1 100.00
lc_ctrl_security_escalation 7.490s 334.122us 1 1 100.00
lc_ctrl_jtag_state_failure 14.240s 860.708us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.570s 268.912us 1 1 100.00
lc_ctrl_jtag_errors 50.820s 3003.521us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 1949.913us 1 1 100.00
lc_ctrl_jtag_state_post_trans 24.120s 1227.967us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.570s 268.912us 1 1 100.00
lc_ctrl_jtag_errors 50.820s 3003.521us 1 1 100.00
lc_ctrl_jtag_access 7.620s 716.435us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 24.540s 1304.518us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.620s 81.044us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.540s 73.840us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.780s 2246.450us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.350s 187.031us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.150s 101.665us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.070s 115.572us 1 1 100.00
lc_ctrl_jtag_alert_test 1.520s 89.547us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.450s 4568.144us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.190s 45.908us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 62.810s 6509.090us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.930s 77.613us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.660s 242.077us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.660s 242.077us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.390s 14.090us 1 1 100.00
lc_ctrl_csr_rw 0.980s 53.726us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 226.091us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.740s 40.760us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.390s 14.090us 1 1 100.00
lc_ctrl_csr_rw 0.980s 53.726us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 226.091us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.740s 40.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
lc_ctrl_tl_intg_err 2.010s 79.419us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.010s 79.419us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.800s 269.021us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.750s 642.726us 1 1 100.00
lc_ctrl_sec_cm 9.980s 1539.455us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.490s 334.122us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.630s 332.180us 1 1 100.00
lc_ctrl_jtag_state_post_trans 24.120s 1227.967us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.150s 1694.161us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.150s 1694.161us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.920s 322.506us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.600s 1160.550us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.600s 1160.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 29.390s 4860.529us 1 1 100.00