Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.98 %
  • code
  • 84.02 %
  • assert
  • 94.97 %
  • func
  • 93.95 %
  • line
  • 97.00 %
  • branch
  • 93.08 %
  • cond
  • 79.34 %
  • toggle
  • 86.19 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.290s 133.054us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 27.038us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.980s 59.128us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.060s 26.472us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 16.175us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.970s 55.966us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.980s 59.128us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 16.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.530s 106.456us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.730s 1380.578us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 23.040us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.810s 189.911us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 12.520s 735.850us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_prog_failure 1.810s 189.911us 1 1 100.00
lc_ctrl_errors 12.520s 735.850us 1 1 100.00
lc_ctrl_security_escalation 7.910s 365.090us 1 1 100.00
lc_ctrl_jtag_state_failure 33.130s 6682.902us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.610s 255.443us 1 1 100.00
lc_ctrl_jtag_errors 15.660s 2188.051us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.120s 416.284us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.900s 1744.606us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.610s 255.443us 1 1 100.00
lc_ctrl_jtag_errors 15.660s 2188.051us 1 1 100.00
lc_ctrl_jtag_access 1.620s 71.155us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.850s 1159.313us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.290s 621.176us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.010s 97.403us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 18.860s 4648.955us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.700s 440.697us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 39.184us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.430s 285.342us 1 1 100.00
lc_ctrl_jtag_alert_test 1.070s 53.669us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.150s 439.331us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 26.156us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 198.390s 16485.352us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.050s 54.578us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.600s 1458.999us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.600s 1458.999us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 27.038us 1 1 100.00
lc_ctrl_csr_rw 0.980s 59.128us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 16.175us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 65.442us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 27.038us 1 1 100.00
lc_ctrl_csr_rw 0.980s 59.128us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 16.175us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 65.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 236.237us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 236.237us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.730s 1380.578us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.440s 4741.058us 1 1 100.00
lc_ctrl_sec_cm 5.730s 265.301us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.910s 365.090us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.530s 106.456us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.900s 1744.606us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.760s 1128.989us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.760s 1128.989us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.270s 771.481us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.560s 1004.488us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.560s 1004.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.271s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
lc_ctrl_stress_all_with_rand_reset 73734116709806671328881806122301375152146463748280299935447610788029543612119 None