Simulation Results: otbn

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.33 %
  • code
  • 80.33 %
  • assert
  • 87.58 %
  • func
  • 94.07 %
  • block
  • 97.65 %
  • line
  • 97.86 %
  • branch
  • 81.47 %
  • toggle
  • 78.59 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 39.385us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 30.000s 43.811us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 30.000s 14.092us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 35.000s 537.643us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 31.000s 24.517us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 32.000s 60.650us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 30.000s 14.092us 1 1 100.00
otbn_csr_aliasing 31.000s 24.517us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 121.000s 11616.414us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 57.000s 2518.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 33.000s 93.616us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 52.000s 979.993us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 33.000s 325.075us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 8.000s 18.312us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 30.000s 23.341us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 7.000s 8.606us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 122.000s 466.880us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 32.000s 25.285us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 25.000s 24.182us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 113.887us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 113.887us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 30.000s 43.811us 1 1 100.00
otbn_csr_rw 30.000s 14.092us 1 1 100.00
otbn_csr_aliasing 31.000s 24.517us 1 1 100.00
otbn_same_csr_outstanding 3.000s 17.264us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 30.000s 43.811us 1 1 100.00
otbn_csr_rw 30.000s 14.092us 1 1 100.00
otbn_csr_aliasing 31.000s 24.517us 1 1 100.00
otbn_same_csr_outstanding 3.000s 17.264us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 32.000s 26.787us 1 1 100.00
otbn_dmem_err 34.000s 33.006us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 36.000s 64.748us 1 1 100.00
otbn_controller_ispr_rdata_err 34.000s 36.237us 1 1 100.00
otbn_mac_bignum_acc_err 24.000s 62.727us 1 1 100.00
otbn_urnd_err 5.000s 26.012us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 27.000s 29.738us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 20.000s 38.464us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 84.500us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
otbn_tl_intg_err 16.000s 211.390us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 44.000s 207.985us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 39.385us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 34.000s 33.006us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 32.000s 26.787us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 211.390us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 30.000s 23.341us 1 1 100.00
sec_cm_controller_fsm_local_esc 3 5 60.00
otbn_imem_err 32.000s 26.787us 1 1 100.00
otbn_dmem_err 34.000s 33.006us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 8.606us 0 1 0.00
otbn_illegal_mem_acc 27.000s 29.738us 1 1 100.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 3 5 60.00
otbn_imem_err 32.000s 26.787us 1 1 100.00
otbn_dmem_err 34.000s 33.006us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 8.606us 0 1 0.00
otbn_illegal_mem_acc 27.000s 29.738us 1 1 100.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 30.000s 23.341us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 3 5 60.00
otbn_imem_err 32.000s 26.787us 1 1 100.00
otbn_dmem_err 34.000s 33.006us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 8.606us 0 1 0.00
otbn_illegal_mem_acc 27.000s 29.738us 1 1 100.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 36.000s 44.690us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 28.780us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 24.000s 264.943us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 24.000s 264.943us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 35.808us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 236.852us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 10.000s 240.480us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 10.000s 240.480us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 12.000s 96.097us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 33.000s 325.075us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 58.191us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 110.592us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 74.775us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 237.000s 4500.161us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 19.100us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_zero_state_err_urnd 100309382613499356364410884683816206619535807273712968325135366677448988385647 109
UVM_ERROR @ 8605905 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8605905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 9132218601940236273662755582534183510364139611730650928066759569472012210452 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 240479693 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 240479693 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 240479693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 80446619689256308035697672696251454230968327152500366423209322245745695668113 497
UVM_INFO @ 4500160519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 7536917838606832588488566661006773596128983346543647731628030970928413872208 135
UVM_ERROR @ 74775421 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 74775421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---