Simulation Results: otp_ctrl

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.36 %
  • code
  • 79.69 %
  • assert
  • 93.99 %
  • func
  • 76.40 %
  • line
  • 88.59 %
  • branch
  • 83.45 %
  • cond
  • 90.32 %
  • toggle
  • 89.92 %
  • FSM
  • 46.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 3.190s 809.103us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.710s 137.092us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.330s 40.464us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.960s 532.613us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 258.799us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.010s 77.912us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.330s 40.464us 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 258.799us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.240s 36.482us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.290s 69.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.230s 3372.007us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.390s 169.493us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 30.300s 9640.925us 1 1 100.00
otp_ctrl_check_fail 12.820s 1216.442us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.050s 490.878us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 3.590s 119.585us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 14.490s 6942.788us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 21.800s 1332.536us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 7.540s 1871.618us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 14.250s 10490.392us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 180.250s 21875.043us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.240s 613.906us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.330s 206.012us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.800s 197.822us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.800s 197.822us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.710s 137.092us 1 1 100.00
otp_ctrl_csr_rw 1.330s 40.464us 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 258.799us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.570s 322.755us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.710s 137.092us 1 1 100.00
otp_ctrl_csr_rw 1.330s 40.464us 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 258.799us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.570s 322.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
otp_ctrl_tl_intg_err 9.770s 1163.165us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 9.770s 1163.165us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_ctrl_macro_errs 7.540s 1871.618us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_ctrl_macro_errs 7.540s 1871.618us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.170s 316.077us 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.390s 169.493us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 12.820s 1216.442us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 7.110s 451.595us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.830s 175526.637us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.050s 490.878us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.340s 317.937us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 7.540s 1871.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.290s 3646.929us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 7.630s 7031.231us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 12644143345430856125542789135882673027735816347368812495395036922502695084461 188
UVM_INFO @ 7031231254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---