Simulation Results: pwrmgr

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.95 %
  • code
  • 91.39 %
  • assert
  • 98.43 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.32 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.690s 32.470us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.730s 29.898us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 25.339us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.830s 402.358us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.970s 67.902us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.720s 52.762us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 25.339us 1 1 100.00
pwrmgr_csr_aliasing 0.970s 67.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.690s 70.924us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.690s 70.924us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.730s 22.032us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 45.655us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 2.020s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.720s 54.892us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.020s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.670s 57.538us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.870s 481.001us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.740s 128.200us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.980s 632.241us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.670s 18.991us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.830s 441.587us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.830s 441.587us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 29.898us 1 1 100.00
pwrmgr_csr_rw 0.690s 25.339us 1 1 100.00
pwrmgr_csr_aliasing 0.970s 67.902us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 56.908us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 29.898us 1 1 100.00
pwrmgr_csr_rw 0.690s 25.339us 1 1 100.00
pwrmgr_csr_aliasing 0.970s 67.902us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 56.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.920s 128.355us 1 1 100.00
pwrmgr_sec_cm 1.590s 666.991us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.590s 666.991us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.590s 666.991us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.920s 128.355us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.550s 1622.692us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.670s 57.538us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.120s 861.839us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.810s 103.275us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.640s 33.534us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.590s 666.991us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.590s 666.991us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.590s 666.991us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 43.295us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.630s 60.195us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.910s 215.589us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 25.339us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 25.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.720s 374.153us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 6.860s 2932.234us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 114346984583722657237738256864918763522934217159931823669501509586101695483511 117
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks 1 test run
pwrmgr_reset_invalid 33462718655272044959104920969045941866596190706039585027084424189308791415626 102
UVM_INFO @ 54892456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---