Simulation Results: rom_ctrl/32kb

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.13 %
  • code
  • 97.11 %
  • assert
  • 97.39 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 97.92 %
  • toggle
  • 95.20 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.660s 404.121us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.580s 129.858us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.460s 553.999us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.610s 123.802us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 1072.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.590s 178.497us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.460s 553.999us 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 1072.156us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.100s 216.809us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.950s 167.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.190s 83.558us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.910s 906.312us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.920s 309.360us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.910s 534.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.330s 288.027us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.330s 288.027us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.580s 129.858us 1 1 100.00
rom_ctrl_csr_rw 3.460s 553.999us 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 1072.156us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.750s 405.630us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.580s 129.858us 1 1 100.00
rom_ctrl_csr_rw 3.460s 553.999us 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 1072.156us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.750s 405.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.970s 4619.937us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 105.580s 699.528us 1 1 100.00
rom_ctrl_tl_intg_err 24.600s 460.477us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 105.580s 699.528us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 105.580s 699.528us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.580s 699.528us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 105.580s 699.528us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.660s 404.121us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.660s 404.121us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.660s 404.121us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.600s 460.477us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
rom_ctrl_kmac_err_chk 8.920s 309.360us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.460s 2822.729us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.970s 4619.937us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.580s 699.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 127.960s 9496.992us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 37199985161109820499370097904092653430658551751785080497441500506642766417898 79
UVM_INFO @ 83558359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---