Simulation Results: rom_ctrl/64kb

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.51 %
  • code
  • 98.09 %
  • assert
  • 97.53 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.03 %
  • toggle
  • 95.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.220s 776.775us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.870s 777.892us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.950s 205.579us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.240s 543.253us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 286.921us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.380s 644.610us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.950s 205.579us 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 286.921us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.730s 298.592us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.260s 1494.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.480s 345.389us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 28.990s 1996.345us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.770s 2102.805us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.320s 289.733us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.360s 297.782us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.360s 297.782us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.870s 777.892us 1 1 100.00
rom_ctrl_csr_rw 7.950s 205.579us 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 286.921us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.190s 320.176us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.870s 777.892us 1 1 100.00
rom_ctrl_csr_rw 7.950s 205.579us 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 286.921us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.190s 320.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.590s 4146.159us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 237.090s 540.030us 1 1 100.00
rom_ctrl_tl_intg_err 53.410s 419.992us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 237.090s 540.030us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 237.090s 540.030us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 237.090s 540.030us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 237.090s 540.030us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.220s 776.775us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.220s 776.775us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.220s 776.775us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.410s 419.992us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
rom_ctrl_kmac_err_chk 13.770s 2102.805us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 126.390s 3871.631us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.590s 4146.159us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 237.090s 540.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 121.640s 18549.077us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 14209945916908682085549596112718038445314279275707650207749816250670884586468 79
UVM_INFO @ 345389295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---