Simulation Results: rstmgr

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.81 %
  • code
  • 99.27 %
  • assert
  • 98.66 %
  • func
  • 98.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 98.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.070s 143.160us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.800s 86.583us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.830s 91.412us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.670s 1451.469us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.380s 232.911us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.040s 117.160us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.830s 91.412us 1 1 100.00
rstmgr_csr_aliasing 1.380s 232.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.840s 161.081us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.300s 588.742us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.340s 279.325us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.410s 1636.922us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.410s 1636.922us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.410s 1636.922us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.410s 1636.922us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 28.590s 13102.512us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.870s 63.371us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.590s 261.075us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.590s 261.075us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 86.583us 1 1 100.00
rstmgr_csr_rw 0.830s 91.412us 1 1 100.00
rstmgr_csr_aliasing 1.380s 232.911us 1 1 100.00
rstmgr_same_csr_outstanding 1.310s 219.693us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 86.583us 1 1 100.00
rstmgr_csr_rw 0.830s 91.412us 1 1 100.00
rstmgr_csr_aliasing 1.380s 232.911us 1 1 100.00
rstmgr_same_csr_outstanding 1.310s 219.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.640s 8430.393us 1 1 100.00
rstmgr_tl_intg_err 2.220s 800.380us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.640s 8430.393us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.640s 8430.393us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.220s 800.380us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.010s 182.940us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.170s 2567.302us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.080s 302.786us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.640s 8430.393us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 91.412us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 91.412us 1 1 100.00