Simulation Results: rv_timer

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.15 %
  • code
  • 99.50 %
  • assert
  • 96.82 %
  • func
  • 89.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 98.77 %
  • toggle
  • 99.22 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.850s 345.709us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 17.930us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 37.663us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.090s 87.306us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.780s 56.595us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.880s 86.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 37.663us 1 1 100.00
rv_timer_csr_aliasing 0.780s 56.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.640s 177.029us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.550s 1268.540us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 154.540s 501954.110us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 154.540s 501954.110us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.340s 2466.579us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 86.514us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 91.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.170s 408.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.170s 408.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 17.930us 1 1 100.00
rv_timer_csr_rw 0.550s 37.663us 1 1 100.00
rv_timer_csr_aliasing 0.780s 56.595us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 56.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 17.930us 1 1 100.00
rv_timer_csr_rw 0.550s 37.663us 1 1 100.00
rv_timer_csr_aliasing 0.780s 56.595us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 56.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.800s 288.369us 1 1 100.00
rv_timer_tl_intg_err 0.740s 179.402us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.740s 179.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.650s 45.362us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.590s 54.410us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 27.030s 29922.299us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 59969376632899362313624858058235446819020616856109579258333131494929846719274 76
UVM_INFO @ 54409686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 89212516788727987651400020541747484738090684038199187698099139915685199682362 76
UVM_INFO @ 177029203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 110220529431415637464637936724844560017649968113027892079896940640518605916170 276
UVM_INFO @ 29922298805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---