Simulation Results: spi_host

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.99 %
  • code
  • 95.03 %
  • assert
  • 95.27 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 6.000s 634.790us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 57.427us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 22.251us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 77.575us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 36.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 25.122us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 22.251us 1 1 100.00
spi_host_csr_aliasing 2.000s 36.497us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 24.431us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 18.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 45.543us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 1.000s 30.594us 1 1 100.00
spi_host_error_cmd 2.000s 23.670us 1 1 100.00
spi_host_event 7.000s 1475.026us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 51.771us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 51.771us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 51.771us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 19.000s 1162.442us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 577.404us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 98.427us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 51.771us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 51.771us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 6.000s 634.790us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 6.000s 634.790us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 12.000s 492.818us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 1696.399us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 21.000s 8044.279us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 395.143us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 1.000s 30.594us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 15.809us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 20.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 38.559us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 38.559us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 57.427us 1 1 100.00
spi_host_csr_rw 2.000s 22.251us 1 1 100.00
spi_host_csr_aliasing 2.000s 36.497us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 35.324us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 57.427us 1 1 100.00
spi_host_csr_rw 2.000s 22.251us 1 1 100.00
spi_host_csr_aliasing 2.000s 36.497us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 35.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 121.270us 1 1 100.00
spi_host_sec_cm 2.000s 165.243us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 121.270us 1 1 100.00