Simulation Results: sram_ctrl/main

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.76 %
  • code
  • 95.91 %
  • assert
  • 97.96 %
  • func
  • 90.40 %
  • block
  • 94.96 %
  • line
  • 95.50 %
  • branch
  • 92.07 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 2092.149us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.211us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.001us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 169.268us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.413us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 354.897us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 18.001us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.413us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 100.000s 14073.474us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 88.000s 9586.557us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 4.000s 3034.430us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 101.000s 3470.305us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 165.000s 218575.892us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 18079.800us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 27.000s 10829.619us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 12636.386us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 366.885us 1 1 100.00
sram_ctrl_partial_access_b2b 148.000s 5903.503us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 2641.675us 0 1 0.00
sram_ctrl_throughput_w_partial_write 6.000s 10990.729us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 1328.346us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 929.380us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 402.578us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 70.000s 84350.163us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.915us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 234.905us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 234.905us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.211us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.001us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.413us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 35.924us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.211us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.001us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.413us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 35.924us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 15.000s 14809.532us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 590.412us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 338.651us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 590.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 338.651us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 929.380us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 929.380us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.001us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 12636.386us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 12636.386us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 12636.386us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 27.000s 10829.619us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 4845.074us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 15.000s 14809.532us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 1356.348us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2092.149us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2092.149us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 12636.386us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 590.412us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 27.000s 10829.619us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 590.412us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 590.412us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 2092.149us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 590.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 65.000s 9221.578us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 109864981690873277172191469124868366728757473068725401878950028834915363769428 86
UVM_INFO @ 2641674706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 34120104968094714068339724470148631945469868744989528846036220735235192115130 86
UVM_INFO @ 10990728699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 96686697220152562437885840492410934109456013469650555992247768997198583905065 86
UVM_INFO @ 1328345582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---