Simulation Results: sysrst_ctrl

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.06 %
  • code
  • 94.31 %
  • assert
  • 96.46 %
  • func
  • 73.41 %
  • line
  • 98.12 %
  • branch
  • 97.96 %
  • cond
  • 95.56 %
  • toggle
  • 99.77 %
  • FSM
  • 80.13 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 5.510s 2112.310us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.820s 2474.161us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.390s 2411.767us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.630s 2544.173us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.950s 4060.325us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2112.706us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 41.850s 30830.335us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 8.190s 3073.302us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.820s 2090.138us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.660s 2112.706us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.190s 3073.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 9.750s 45131.085us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 15.270s 66087.644us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 52.070s 60490.523us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.900s 3349.243us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.660s 2520.315us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.490s 2181.291us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.160s 3341.019us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.490s 2656.855us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.220s 391957.146us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 22.590s 36815.562us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 60.270s 143570.647us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.030s 2035.888us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.720s 2014.541us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.820s 2275.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.820s 2275.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.950s 4060.325us 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2112.706us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.190s 3073.302us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.810s 4376.002us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.950s 4060.325us 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2112.706us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.190s 3073.302us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.810s 4376.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 19.220s 22028.894us 1 1 100.00
sysrst_ctrl_tl_intg_err 43.450s 42396.976us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 43.450s 42396.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.770s 10089.969us 1 1 100.00