Simulation Results: uart

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.75 %
  • code
  • 90.78 %
  • assert
  • 98.85 %
  • func
  • 49.63 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.82 %
  • toggle
  • 73.93 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.730s 5955.406us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 17.524us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.570s 57.428us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.470s 47.110us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.710s 54.399us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 132.870us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.570s 57.428us 1 1 100.00
uart_csr_aliasing 0.710s 54.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 26.420s 68781.894us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.730s 5955.406us 1 1 100.00
uart_tx_rx 26.420s 68781.894us 1 1 100.00
parity_error 2 2 100.00
uart_intr 430.220s 492668.048us 1 1 100.00
uart_rx_parity_err 25.960s 109266.149us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 26.420s 68781.894us 1 1 100.00
uart_intr 430.220s 492668.048us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 234.280s 144218.854us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 48.050s 190142.917us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 64.400s 73055.565us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 430.220s 492668.048us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 430.220s 492668.048us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 430.220s 492668.048us 1 1 100.00
perf 1 1 100.00
uart_perf 142.400s 20053.625us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.720s 2596.305us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.720s 2596.305us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.880s 13756.503us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.610s 5098.370us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 17.860s 7166.972us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 33.850s 7594.381us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 110.490s 168792.494us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 243.740s 243080.468us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.640s 36.331us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.600s 13.615us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.560s 210.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.560s 210.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 17.524us 1 1 100.00
uart_csr_rw 0.570s 57.428us 1 1 100.00
uart_csr_aliasing 0.710s 54.399us 1 1 100.00
uart_same_csr_outstanding 0.870s 116.065us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 17.524us 1 1 100.00
uart_csr_rw 0.570s 57.428us 1 1 100.00
uart_csr_aliasing 0.710s 54.399us 1 1 100.00
uart_same_csr_outstanding 0.870s 116.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.730s 110.941us 1 1 100.00
uart_tl_intg_err 0.790s 479.547us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.790s 479.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 27.190s 6782.660us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 2 test runs
uart_stress_all_with_rand_reset 81952954699233686590778455883379416775474981913762977493834869038242683184715 178
UVM_ERROR @ 5563034818 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 5563059818 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 5686234818 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 5686234818 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 36433087212551781432956468379379612940899812198401581892322926925135340065207 134
UVM_ERROR @ 242590124524 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 242590175544 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (169 [0xa9] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 242590195952 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 242590236768 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (169 [0xa9] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 59423476994958881256907365999054182143006634907836384346489098565609899192305 75
UVM_ERROR @ 10144378300 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10152878300 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10, clk_pulses: 0
UVM_ERROR @ 10153128300 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10154128300 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata