Simulation Results: adc_ctrl

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.44 %
  • code
  • 91.41 %
  • assert
  • 92.06 %
  • func
  • 12.84 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 85.65 %
  • toggle
  • 98.82 %
  • FSM
  • 78.38 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.940s 5827.680us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.350s 1144.121us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.870s 482.540us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 57.980s 51929.539us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.540s 903.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.910s 942.806us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.870s 482.540us 1 1 100.00
adc_ctrl_csr_aliasing 2.540s 903.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.890s 433.364us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.120s 434.695us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.820s 377.838us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.720s 365.709us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.760s 430.627us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.750s 377.375us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.060s 368.383us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.030s 377.183us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.820s 4957.112us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 31.410s 40275.982us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 28.900s 97901.845us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 2.800s 1541.888us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.660s 538.607us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.720s 450.383us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.400s 415.514us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.400s 415.514us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.350s 1144.121us 1 1 100.00
adc_ctrl_csr_rw 0.870s 482.540us 1 1 100.00
adc_ctrl_csr_aliasing 2.540s 903.763us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.650s 4948.433us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.350s 1144.121us 1 1 100.00
adc_ctrl_csr_rw 0.870s 482.540us 1 1 100.00
adc_ctrl_csr_aliasing 2.540s 903.763us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.650s 4948.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.560s 7873.848us 1 1 100.00
adc_ctrl_tl_intg_err 6.460s 4597.222us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.460s 4597.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.640s 672.941us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 11330236553940107045299403965199724064091388543119527431248949351207303936001 386
UVM_INFO @ 433363734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 110027472605385315549632408680040030510086031445070270064617630581336902054468 386
UVM_INFO @ 434694705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 12546923739542919319834938894751541228805950916364322549980975874000898057820 386
UVM_INFO @ 377837587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 14118387691283669798702172996012772272060133749496668526641309116040850355145 386
UVM_INFO @ 365709318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 14809490969183119208428953279063235795241825112145759810058020085223037973100 386
UVM_INFO @ 430627241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 90941013083661369601125025868893320259587438443828980493529793058855986647375 386
UVM_INFO @ 377374854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 110938037139151128123317376077480479751852665587388616992170178410903723035775 386
UVM_INFO @ 377183091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 49846599262671882945535319315500919229480675663351875467886002634822821687489 386
UVM_INFO @ 368383355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 71482048708748456438998248587031964638617626835062127869965904862418240779704 392
UVM_INFO @ 672940955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 26787585625793701967198416133996781568222941718533945936842480178123428530316 410
UVM_INFO @ 1541887863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---