Simulation Results: aes/unmasked

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.73 %
  • code
  • 89.03 %
  • assert
  • 97.73 %
  • func
  • 73.42 %
  • block
  • 89.45 %
  • line
  • 91.95 %
  • branch
  • 79.50 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 80.278us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 91.370us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 58.776us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 63.319us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 260.340us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 541.111us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 108.948us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 63.319us 1 1 100.00
aes_csr_aliasing 3.000s 541.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 91.370us 1 1 100.00
aes_config_error 2.000s 347.014us 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 91.370us 1 1 100.00
aes_config_error 2.000s 347.014us 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 80.324us 1 1 100.00
aes_b2b 5.000s 411.281us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 91.370us 1 1 100.00
aes_config_error 2.000s 347.014us 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
aes_alert_reset 2.000s 487.868us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 198.927us 1 1 100.00
aes_config_error 2.000s 347.014us 1 1 100.00
aes_alert_reset 2.000s 487.868us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 117.608us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 1420.057us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 487.868us 1 1 100.00
stress 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 80.324us 1 1 100.00
aes_sideload 3.000s 102.534us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 68.296us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 11.000s 359.324us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 71.800us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 153.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 153.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.776us 1 1 100.00
aes_csr_rw 2.000s 63.319us 1 1 100.00
aes_csr_aliasing 3.000s 541.111us 1 1 100.00
aes_same_csr_outstanding 1.000s 112.846us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.776us 1 1 100.00
aes_csr_rw 2.000s 63.319us 1 1 100.00
aes_csr_aliasing 3.000s 541.111us 1 1 100.00
aes_same_csr_outstanding 1.000s 112.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 31.898us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 215.957us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1651.693us 1 1 100.00
aes_tl_intg_err 2.000s 631.427us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 631.427us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 487.868us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 91.370us 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
aes_alert_reset 2.000s 487.868us 1 1 100.00
aes_core_fi 2.000s 84.902us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 347.014us 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
aes_core_fi 2.000s 84.902us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 121.887us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 90.335us 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 80.324us 1 1 100.00
aes_sideload 3.000s 102.534us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.335us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.335us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 90.335us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 90.335us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 90.335us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 80.324us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 125.215us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
aes_ctr_fi 2.000s 64.164us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 125.215us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 125.215us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_ctr_fi 2.000s 64.164us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 125.215us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
aes_ctr_fi 2.000s 64.164us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 487.868us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
aes_ctr_fi 2.000s 64.164us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
aes_ctr_fi 2.000s 64.164us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_ctr_fi 2.000s 64.164us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 125.215us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 125.215us 0 1 0.00
aes_control_fi 2.000s 114.355us 1 1 100.00
aes_cipher_fi 1.000s 85.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 12.000s 901.941us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 103108204067824855836633432006058857956083222888692751598550973161979040533143 1235
UVM_INFO @ 31897788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 43189952269710268351772582567352420840052987117573828279365017456254928230367 8129
UVM_INFO @ 359324048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 26182950967272376143873847109471630839302779863885336708045745144154481572545 551
UVM_INFO @ 901941253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 36848053268969755129996246894990599973539162358555199096028353951220567999582 8113
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0