Simulation Results

Simulation Results: chip

29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.21 %

code
84.67 %

assert
97.49 %

func
58.48 %

line
94.54 %

branch
93.94 %

cond
90.47 %

toggle
87.26 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		77.26%
V2S		100.00%
V3		65.38%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	138.900s	2733.146us	1	1	100.00
	chip_sw_example_rom	77.640s	2743.578us	1	1	100.00
	chip_sw_example_manufacturer	125.210s	2577.582us	1	1	100.00
	chip_sw_example_concurrency	162.310s	3105.799us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	175.250s	4303.820us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	282.220s	3611.152us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	1928.040s	31311.907us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3913.560s	34214.083us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	319.760s	5730.197us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3913.560s	34214.083us	1	1	100.00
	chip_csr_rw	282.220s	3611.152us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.330s	51.113us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	357.800s	4085.222us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	357.800s	4085.222us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	357.800s	4085.222us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	338.070s	4944.563us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	338.070s	4944.563us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	364.240s	4588.684us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	412.770s	5075.994us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	357.500s	4462.512us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1024.250s	8479.789us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1778.380s	13069.030us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1031.110s	13917.731us	1	1	100.00

214/277 passed

77.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	220.170s	4795.158us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	220.170s	4795.158us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	216.390s	3403.930us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	157.820s	3165.896us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	177.530s	3496.630us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	735.810s	11409.218us	1	1	100.00
	chip_tap_straps_testunlock0	409.630s	7061.193us	1	1	100.00
	chip_tap_straps_rma	167.010s	3469.857us	1	1	100.00
	chip_tap_straps_prod	208.170s	4874.712us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	503.940s	5975.374us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	503.940s	5975.374us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	689.050s	8087.201us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1486.650s	13224.406us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	394.300s	4148.391us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	659.730s	6255.688us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4091.090s	20004.264us	1	1	100.00
	chip_sw_aes_enc_jitter_en	172.810s	3322.389us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	790.820s	6847.946us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.300s	2769.920us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1180.690s	10129.886us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	195.940s	3353.251us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	327.910s	5275.362us	1	1	100.00
	chip_sw_clkmgr_jitter	196.090s	3718.442us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	242.650s	3987.349us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	456.070s	5933.655us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	266.460s	5125.340us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	189.320s	3583.453us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	266.460s	5125.340us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	181.410s	3432.301us	1	1	100.00
	chip_sw_aes_smoketest	177.040s	2702.463us	1	1	100.00
	chip_sw_aon_timer_smoketest	211.820s	3469.477us	1	1	100.00
	chip_sw_clkmgr_smoketest	110.430s	2828.620us	1	1	100.00
	chip_sw_csrng_smoketest	128.430s	2515.866us	1	1	100.00
	chip_sw_entropy_src_smoketest	684.410s	6149.816us	1	1	100.00
	chip_sw_gpio_smoketest	211.730s	3582.129us	1	1	100.00
	chip_sw_hmac_smoketest	233.680s	3682.631us	1	1	100.00
	chip_sw_kmac_smoketest	225.260s	3742.303us	1	1	100.00
	chip_sw_otbn_smoketest	605.350s	4773.323us	1	1	100.00
	chip_sw_pwrmgr_smoketest	315.050s	6301.240us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	260.930s	5206.405us	1	1	100.00
	chip_sw_rv_plic_smoketest	176.890s	2710.517us	1	1	100.00
	chip_sw_rv_timer_smoketest	179.610s	3433.483us	1	1	100.00
	chip_sw_rstmgr_smoketest	156.270s	3294.876us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	131.400s	2973.368us	1	1	100.00
	chip_sw_uart_smoketest	154.910s	2551.416us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	121.260s	3327.412us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	373.280s	5938.568us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7707.100s	64502.696us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3086.580s	17215.175us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	34.712s	0.000us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	428.910s	4372.285us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	183.120s	4256.655us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7370.600s	54951.741us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7316.360s	58269.430us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	212.590s	4683.687us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	212.590s	4683.687us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3913.560s	34214.083us	1	1	100.00
	chip_same_csr_outstanding	1084.990s	13340.227us	1	1	100.00
	chip_csr_hw_reset	175.250s	4303.820us	1	1	100.00
	chip_csr_rw	282.220s	3611.152us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3913.560s	34214.083us	1	1	100.00
	chip_same_csr_outstanding	1084.990s	13340.227us	1	1	100.00
	chip_csr_hw_reset	175.250s	4303.820us	1	1	100.00
	chip_csr_rw	282.220s	3611.152us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	28.740s	521.824us	1	1	100.00
xbar_random_delay				5	6	83.33
	xbar_smoke_zero_delays	4.410s	48.432us	1	1	100.00
	xbar_smoke_large_delays	35.710s	6592.356us	1	1	100.00
	xbar_smoke_slow_rsp	38.040s	4540.154us	1	1	100.00
	xbar_random_zero_delays	91.148s	0.000us	0	1	0.00
	xbar_random_large_delays	120.640s	22109.530us	1	1	100.00
	xbar_random_slow_rsp	105.770s	11147.933us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	43.870s	1474.074us	1	1	100.00
	xbar_error_and_unmapped_addr	32.410s	1196.472us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	36.970s	1719.248us	1	1	100.00
	xbar_error_and_unmapped_addr	32.410s	1196.472us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	37.830s	1378.385us	1	1	100.00
	xbar_access_same_device_slow_rsp	367.780s	45948.485us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	7.550s	120.176us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	181.260s	3181.819us	1	1	100.00
	xbar_stress_all_with_error	162.550s	6714.150us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	155.400s	3940.579us	1	1	100.00
	xbar_stress_all_with_reset_error	501.360s	8615.471us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3086.580s	17215.175us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	1674.030s	26264.634us	0	1	0.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3152.670s	15666.995us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	40.376s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	43.205s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	21.584s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	53.523s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	21.853s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	111.161s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.890s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	46.499s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	21.226s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	71.634s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	119.358s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	45.221s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.096s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	43.691s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	44.208s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.080s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	18.540s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.990s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.270s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	19.810s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.990s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.500s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.170s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	21.010s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.320s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.000s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.720s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.780s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.920s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	20.190s	10.260us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	123.893s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	44.806s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	35.668s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	22.316s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	46.930s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5859.490s	28872.529us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5806.520s	28868.142us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	3076.220s	18471.728us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3195.100s	16031.787us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3103.980s	34163.937us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3103.980s	34163.937us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	200.540s	2910.311us	1	1	100.00
	chip_sw_aes_enc_jitter_en	172.810s	3322.389us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	182.650s	3712.882us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	148.650s	2671.332us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1641.580s	13040.084us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	228.480s	3338.361us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	392.370s	6009.131us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	613.120s	5572.551us	1	1	100.00
	chip_plic_all_irqs_10	249.800s	3988.111us	1	1	100.00
	chip_plic_all_irqs_20	384.760s	3967.537us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	167.000s	3510.648us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1207.890s	14234.595us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	236.100s	4068.228us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	160.110s	3395.032us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.138s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1230.780s	9480.233us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1161.480s	8294.856us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	758.390s	7731.305us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8757.020s	255588.743us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	255.300s	3806.797us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	315.050s	6301.240us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	255.300s	3806.797us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	415.620s	7266.214us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	415.620s	7266.214us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	301.850s	7366.998us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	425.140s	5389.019us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	645.220s	6113.650us	1	1	100.00
	chip_sw_aes_idle	148.650s	2671.332us	1	1	100.00
	chip_sw_hmac_enc_idle	138.250s	2540.078us	1	1	100.00
	chip_sw_kmac_idle	156.490s	2855.062us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	240.930s	3967.157us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	282.680s	4461.626us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	251.930s	5240.580us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	317.580s	4547.072us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	830.660s	12960.831us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	354.490s	3922.624us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	403.930s	4613.270us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	382.810s	4050.055us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	382.700s	5167.857us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	373.820s	3775.013us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	397.840s	5058.429us	1	1	100.00
	chip_sw_ast_clk_outputs	689.050s	8087.201us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	285.580s	6716.086us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	382.810s	4050.055us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	382.700s	5167.857us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	394.300s	4148.391us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	659.730s	6255.688us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4091.090s	20004.264us	1	1	100.00
	chip_sw_aes_enc_jitter_en	172.810s	3322.389us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	790.820s	6847.946us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.300s	2769.920us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1180.690s	10129.886us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	195.940s	3353.251us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	327.910s	5275.362us	1	1	100.00
	chip_sw_clkmgr_jitter	196.090s	3718.442us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	173.910s	3327.033us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	355.710s	4805.992us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	717.460s	6985.731us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4417.000s	25543.777us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	180.860s	3431.045us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	157.680s	3041.734us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	597.690s	7113.997us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	157.010s	3585.077us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	386.840s	6377.153us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1136.470s	23200.701us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	9722.330s	99421.627us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	689.050s	8087.201us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	407.650s	4833.946us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	276.630s	3764.533us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1230.780s	9480.233us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2236.840s	24474.588us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	302.140s	4082.344us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	435.210s	6907.417us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	203.390s	3127.403us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	1716.360s	10769.272us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	159.310s	3025.271us	1	1	100.00
	chip_sw_edn_entropy_reqs	665.540s	7839.915us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	159.310s	3025.271us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2236.840s	24474.588us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	178.140s	3040.872us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1160.820s	18979.084us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	632.840s	5896.416us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	659.730s	6255.688us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	326.570s	3936.197us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	394.300s	4148.391us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3470.030s	43303.256us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1160.820s	18979.084us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	214.990s	3899.338us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	770.440s	7640.301us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	191.140s	3057.180us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3470.030s	43303.256us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	191.140s	3057.180us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	191.140s	3057.180us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	191.140s	3057.180us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	191.140s	3057.180us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	319.370s	11719.732us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	561.350s	5402.488us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	415.210s	6102.775us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	415.210s	6102.775us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	166.610s	3037.523us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.300s	2769.920us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	138.250s	2540.078us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1277.410s	10117.995us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1609.760s	12018.424us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	327.120s	4212.288us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	378.820s	4792.290us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	423.900s	4965.533us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	267.490s	3508.324us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	770.440s	7640.301us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1180.690s	10129.886us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1408.250s	10744.692us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1641.580s	13040.084us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4930.780s	20026.774us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	175.580s	2929.104us	1	1	100.00
	chip_sw_kmac_mode_kmac	210.520s	3433.210us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	195.940s	3353.251us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	770.440s	7640.301us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	201.930s	3154.122us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	492.520s	4406.418us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	156.490s	2855.062us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	392.370s	6009.131us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	735.810s	11409.218us	1	1	100.00
	chip_tap_straps_rma	167.010s	3469.857us	1	1	100.00
	chip_tap_straps_prod	208.170s	4874.712us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	172.570s	2995.779us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1803.430s	13242.598us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	191.140s	3057.180us	0	1	0.00
	chip_sw_flash_rma_unlocked	3470.030s	43303.256us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	220.990s	3913.680us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	598.400s	6302.340us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	508.080s	7582.002us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	492.910s	6436.429us	0	1	0.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
	chip_sw_keymgr_key_derivation	770.440s	7640.301us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	361.300s	9515.368us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	477.590s	8299.102us	1	1	100.00
	chip_prim_tl_access	319.370s	11719.732us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	285.580s	6716.086us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	354.490s	3922.624us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	403.930s	4613.270us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	382.810s	4050.055us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	382.700s	5167.857us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	373.820s	3775.013us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	397.840s	5058.429us	1	1	100.00
	chip_tap_straps_dev	735.810s	11409.218us	1	1	100.00
	chip_tap_straps_rma	167.010s	3469.857us	1	1	100.00
	chip_tap_straps_prod	208.170s	4874.712us	1	1	100.00
	chip_rv_dm_lc_disabled	73.820s	3590.181us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	172.910s	3533.298us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	79.790s	3640.457us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	114.770s	3301.707us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	94.120s	2431.006us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1964.570s	34215.643us	1	1	100.00
	chip_rv_dm_lc_disabled	73.820s	3590.181us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	565.780s	8309.132us	0	1	0.00
	chip_sw_lc_walkthrough_prod	707.180s	11054.404us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	720.370s	9150.972us	1	1	100.00
	chip_sw_lc_walkthrough_rma	371.500s	5531.215us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1964.570s	34215.643us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	59.800s	2158.302us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	59.040s	2322.848us	1	1	100.00
	rom_volatile_raw_unlock	97.234s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3958.920s	17715.730us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4091.090s	20004.264us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	645.220s	6113.650us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	645.220s	6113.650us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	645.220s	6113.650us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	259.110s	3711.310us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1160.820s	18979.084us	1	1	100.00
	chip_sw_otbn_mem_scramble	259.110s	3711.310us	1	1	100.00
	chip_sw_keymgr_key_derivation	770.440s	7640.301us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	295.140s	3728.212us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.700s	2805.172us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1160.820s	18979.084us	1	1	100.00
	chip_sw_otbn_mem_scramble	259.110s	3711.310us	1	1	100.00
	chip_sw_keymgr_key_derivation	770.440s	7640.301us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	295.140s	3728.212us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.700s	2805.172us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	303.740s	5111.696us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	172.570s	2995.779us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	220.990s	3913.680us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	598.400s	6302.340us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	508.080s	7582.002us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	492.910s	6436.429us	0	1	0.00
	chip_sw_lc_ctrl_transition	434.820s	7760.817us	1	1	100.00
	chip_prim_tl_access	319.370s	11719.732us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	319.370s	11719.732us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	943.820s	7344.650us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	185.860s	6076.827us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	909.640s	25463.587us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	210.610s	7827.547us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	311.890s	7374.262us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	477.760s	8490.651us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	776.430s	25250.012us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	245.550s	5632.996us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	415.620s	7266.214us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	833.490s	12314.067us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	298.180s	3681.460us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	185.860s	6076.827us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	230.630s	3840.577us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	319.610s	7047.898us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	292.570s	6034.592us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	156.590s	2886.152us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	192.470s	5556.088us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	765.320s	8082.269us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	731.740s	10665.901us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1338.530s	25019.005us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	204.390s	3538.227us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	361.300s	9515.368us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	361.300s	9515.368us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	731.740s	10665.901us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	192.470s	5556.088us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	298.180s	3681.460us	1	1	100.00
	chip_sw_pwrmgr_smoketest	315.050s	6301.240us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	270.930s	3920.437us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	312.420s	5740.653us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	333.400s	4949.444us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1207.890s	14234.595us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	144.800s	2943.024us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1161.480s	8294.856us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	470.070s	4634.292us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	491.060s	4765.499us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	208.950s	3192.887us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.700s	2805.172us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	312.420s	5740.653us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	312.420s	5740.653us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	124.090s	2758.334us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1159.690s	17179.671us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	930.140s	14389.700us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	270.930s	3920.437us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	194.690s	3153.976us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	287.060s	5658.033us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	167.010s	3469.857us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	73.820s	3590.181us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	613.120s	5572.551us	1	1	100.00
	chip_plic_all_irqs_10	249.800s	3988.111us	1	1	100.00
	chip_plic_all_irqs_20	384.760s	3967.537us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	127.260s	2657.908us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	151.350s	2689.615us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3086.580s	17215.175us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	219.520s	3426.076us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	217.400s	3874.497us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	251.450s	3755.120us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	195.510s	3559.667us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	295.140s	3728.212us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	327.910s	5275.362us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	401.030s	8703.853us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	422.700s	7106.451us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	477.590s	8299.102us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
	chip_sw_data_integrity_escalation	503.940s	5975.374us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	765.320s	8082.269us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1076.110s	22614.552us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	171.880s	2690.121us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	243.510s	4130.209us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	299.870s	4489.238us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1076.110s	22614.552us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1076.110s	22614.552us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2373.020s	20566.072us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2373.020s	20566.072us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	299.010s	6056.376us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3103.980s	34163.937us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	140.760s	2849.818us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	173.110s	2780.737us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	322.900s	4633.527us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	326.230s	3440.338us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	938.280s	7830.076us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5151.450s	31531.086us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1892.820s	11901.259us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	154.290s	3490.313us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	174.760s	3178.068us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	188.120s	2968.000us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10115.820s	72206.781us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1144.730s	6466.502us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	194.760s	4004.903us	0	1	0.00
	rom_e2e_jtag_debug_dev	193.960s	5142.147us	0	1	0.00
	rom_e2e_jtag_debug_rma	431.350s	7300.242us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	283.890s	5431.851us	1	1	100.00
	rom_e2e_jtag_inject_dev	60.420s	2023.635us	0	1	0.00
	rom_e2e_jtag_inject_rma	239.970s	4034.301us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	104.647s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	299.460s	3409.202us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	322.020s	2912.837us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	512.110s	4074.227us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1440.040s	10911.675us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	224.940s	3110.852us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	593.020s	5375.513us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	135.170s	3482.988us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	176.690s	2800.906us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	277.220s	6548.897us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	389.240s	5040.432us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	731.740s	10665.901us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	194.760s	4004.903us	0	1	0.00
	rom_e2e_jtag_debug_dev	193.960s	5142.147us	0	1	0.00
	rom_e2e_jtag_debug_rma	431.350s	7300.242us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	328.620s	5535.495us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	477.790s	6475.132us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5709.790s	38128.834us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5709.790s	38128.834us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	62.760s	0.000us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	338.070s	4944.563us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3179.440s	18733.109us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	224.020s	3370.776us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	20.390s	10.120us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.220s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	131.670s	2782.255us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	213.180s	3304.002us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	259.620s	4251.136us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.406s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	218.420s	4040.873us	1	1	100.00
	ate_bootstrap_flash_erase	580.150s	10010.200us	0	1	0.00
	ate_bootstrap_one_frame	6439.480s	45324.582us	1	1	100.00
	ate_bootstrap_disjoint	9673.100s	84997.725us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				26 test runs
	chip_sw_spi_device_pinmux_sleep_retention	27240054841658471319709641954038627553887415790581093734095307131607772712496	None	Chronologic VCS simulator copyright 1991-2023 Contains Synopsys proprietary information. Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jun 29 16:49 2026 Feature removed during lmreread, or wrong SERVER line hostid. Check your license file. Please contact VCS Customer Support at 1-800-VERILOG for more information. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
	chip_sw_pwrmgr_sleep_wake_5_bug	108151393845477411901557244092908563800571187815525134238401394044665211184260	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	19527295158034707990834874969904545715626784596668928363458882579832048502641	None	---- STDERR ---- Another command (pid=372568) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=397843) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	95712477128488536586635593444451713132960124935404892894776592060902318676316	None	Another command (pid=676527) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=665451) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=689739) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	64487776026294447381506398985424797166142619330701601085919765602962900460495	None	Another command (pid=625062) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=631217) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=570624) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	95016985206936345810214932590212420473689326710150132925739655355112917683337	None	Another command (pid=710105) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=679762) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=712090) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	17599724333222231085701112703641414190630598904521743546523799106565240248420	None	Another command (pid=594915) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=636826) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=604758) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	93786680608962441601006882606196988878778739129277270449604955531003389562101	None	Another command (pid=387218) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=556939) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=554067) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	71279245963551649509081668687855914904869830233987297947009329245476289283011	None	---- STDERR ---- Another command (pid=573520) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=569635) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	63455546385678910337883122427116725771510599386565623782291168225527847049950	None	Another command (pid=650445) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=646267) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=555019) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	30752053378470728433580628439732967530543602134591786451093484804769545393230	None	Another command (pid=573226) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=593789) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=564280) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	66632559875581598179480841653200534091108333367400721649314298992708269981622	None	Another command (pid=710105) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=679762) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=712090) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	54142207529375188029268194857726952192819639678747443407621425807867807783694	None	Another command (pid=463250) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=551309) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=387218) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	26525824909836263203774083266247069128609341815637448171735187782642738284571	None	Another command (pid=632443) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=635931) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=636826) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	94501838381740748352896868804308447424758070855150548290116838632751900789054	None	Another command (pid=569635) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=577800) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=574963) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	19748599343287355696366067324368153933759461063275847147058363270633301198143	None	Another command (pid=608351) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=595526) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=635931) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	93383186538340460526124741288832413889564270822873590431236149361159137684185	None	Another command (pid=636826) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=604758) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=616595) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	73136659753700673385190226099738135728432522932466502574392914776921858852285	None	Another command (pid=375622) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=460703) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=435020) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	83873119094474637678732065202080331816527679954395328960796752180195437503899	None	---- STDERR ---- Another command (pid=460703) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=435020) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	41398183080432847555474052481684467967296487579059481697030836167053283660797	None	Another command (pid=460703) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=435020) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=375126) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	22730249824935300815945840183461125030900670464049407171041878187931225709161	None	Another command (pid=516545) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=551309) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=387218) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	102513449447991272048205201973043418005822614632810472504289175814990947085622	None	Another command (pid=604758) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=649323) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=616595) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	36367514213560192441486818887131091002514912946985359553622016285417561494494	None	Another command (pid=387218) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=556939) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=554067) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	49675137429385702179347412121931321271030031948592426555037150376887880680608	None	---- STDERR ---- Another command (pid=372568) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=397843) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	47130428178353067644696620171955968358441214079223887216272315061225871104829	None	Another command (pid=516545) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=551309) is running. Waiting for it to complete on the server (server_pid=273171)... Another command (pid=387218) is running. Waiting for it to complete on the server (server_pid=273171)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	xbar_random_zero_delays	6366604327455744053908806023126181501122123677017460347166649338385805035456	None	Chronologic VCS simulator copyright 1991-2023 Contains Synopsys proprietary information. Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jun 29 16:55 2026 Feature removed during lmreread, or wrong SERVER line hostid. Check your license file. Please contact VCS Customer Support at 1-800-VERILOG for more information. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	26489918119120380908062782787211585434341236724186185803727023457038818772597	368	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	84153114275926046240032914661910326574848456715596397433990648523989884226683	367	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	111490345097144908214728733912648469005630339003976502162655256661654660369779	367	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	36521472622845035878493489363369752737825328616566911672251351721045309592357	327	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19687523750302629153898811179610727169882190084554750525255631829786779257635	326	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	16716629768480846512414493390835556296072667960431479120349623230666655768033	328	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	112159934023198659803065064626806278302270555773422682216530379189501709338212	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	30738798548618555558163158288786584639478487767968357949639444221563228996931	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	35942894436888783829597651937468030276006889956154506292908334431666201175323	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	75091747211937253549093583692786381271467675569545867998268018775376577357105	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	90262567261896564471142121007582067247302163302855459504697981044480740469120	310	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))'				4 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	105267351626645721791588326385923337359833529885064289748400901433037316752057	315	UVM_ERROR @ 5556.088500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5556.088500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	36861194536984705483594651591059572124646484751308683184176865694376951602309	314	UVM_ERROR @ 5632.996000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5632.996000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	11657703794255412815624741838705315894910006990989263288346167558401695847276	325	UVM_ERROR @ 7374.262000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7374.262000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	106057563052854811214384497192774361165196579676820955660719968255350427253245	319	UVM_ERROR @ 7266.214000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7266.214000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	64543255752908561408836124310201420916934727469461794745594581372251144552841	369	UVM_INFO @ 8309.132362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	83636040188538957039677346248710542172320742232227252899336182580601106854020	369	UVM_INFO @ 11054.403918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	14633073806817644126302383391150267350497852321859871329776610198774114377813	341	UVM_INFO @ 5531.215448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	93127527582124742644055139972435693418536543982083587080028478170973720743523	326	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16286656077225245165275060961432686884131820863039019883680925637457722656641	327	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	55704872369080491400499725278381800587290256370482762002394836744263036282362	325	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	54514408994085176670584283235674776023235507773948433485357840285285460558848	313	UVM_ERROR @ 2886.151695 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2886.151695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	23047037866732774117400668154462273560411667352438383922533035448653510234713	327	UVM_ERROR @ 7047.897639 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 7047.897639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	109271976247557461190045103649161795560290003178557031239112185099143899198942	337	UVM_INFO @ 12018.424084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	14496051187136450160112463229837826395381083044121803022864033180347813060878	336	UVM_INFO @ 20026.774326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	82756661321856364289763035154619329472823593146677155816451874259124728430837	363	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12955654593848625250629401398977391034121744567411095257341544691946133325099	325	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	45452001703819737371044708317321773211785716950650734899749701095850875945510	368	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	105502723010580561908081437915415845241540122760183494456064204211792380224563	327	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	24288937064124406244673168034152132895114866886659925463382954053053950118791	301	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	21731889764118445760438051722454713905560392802376108553727011183873350047157	327	UVM_INFO @ 3874.497455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	103855754770588996371986550128480303799044764380331353352374868083390314750755	309	UVM_INFO @ 3057.179500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	53118952015273341485534345277501337345877320281319351645389441173194986949551	342	UVM_INFO @ 6436.428808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	46060759489253333348060585553129319508536312810909917632956265975211315312476	316	UVM_ERROR @ 2800.905876 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2800.905876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	6917516888775617135689184288883559908308524057453210507112939754712979796000	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	95730400244186812025609269101321258891535483123559616573130434657054951866215	322	UVM_ERROR @ 6076.826852 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 6076.826852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	62851608835392451525608752909550734016974696048616961968972597551840936868231	332	UVM_INFO @ 34163.937113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:297)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	32834869886154748274123966347597308448824378023836468918312588223484033438660	307	UVM_INFO @ 3338.361022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	11233223706874658735637264698664101417231031639061237117699588277727253501903	308	UVM_INFO @ 3395.032486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	67661757438305457537893199150526304428764862678201100996044489120838792001377	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	10504520113652822199298667986771340340023371512544331879043335238604890339476	343	UVM_INFO @ 3409.202401 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	70165302581041231232697111313231934611199460018982604536239574695507432313980	225	UVM_INFO @ 3590.181098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	42619169874031986752503799797057520739752219635558060990126976166462372949745	327	UVM_INFO @ 13224.405597 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	20043081640783536016536387460545476778775415317527997288261797725138569981574	272	UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!				1 test run
	rom_e2e_shutdown_output	47027174601456339138648288857480750965433474522031605731500146634514639597263	329	UVM_INFO @ 26264.634175 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	365343339854044057128363723878890829099922021760708196511498216171410053379	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	104350581599496353565008193982091312468203703258202614011990329351584577392781	326	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [] vs [*])				1 test run
	rom_e2e_jtag_debug_test_unlocked0	78717783253770231313636424835318626876051635654634863940367374033310516670875	317	UVM_INFO @ 4004.903150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_invalid_meas	110011184070658154248148710779965314585087289271873763677735182300988848187359	319	UVM_INFO @ 18471.728450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	18067650442868868314853427004937758118825253122724686284462544481191965579569	327	UVM_ERROR @ 5938.567999 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 5938.567999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---