Simulation Results: clkmgr

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.32 %
  • code
  • 97.94 %
  • assert
  • 94.63 %
  • func
  • 84.39 %
  • line
  • 98.97 %
  • branch
  • 98.64 %
  • cond
  • 92.90 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.330s 148.910us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.980s 49.063us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.400s 786.300us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.490s 142.141us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.180s 95.475us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
clkmgr_csr_aliasing 1.490s 142.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.670s 18.902us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.760s 42.256us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 33.556us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.910s 60.871us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.330s 148.910us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.410s 2149.838us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.490s 2201.883us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.410s 2149.838us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 39.100s 19696.606us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 28.324us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.110s 1204.163us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.110s 1204.163us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.980s 49.063us 1 1 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
clkmgr_csr_aliasing 1.490s 142.141us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 37.829us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.980s 49.063us 1 1 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
clkmgr_csr_aliasing 1.490s 142.141us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 37.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.800s 13.530us 0 1 0.00
clkmgr_tl_intg_err 2.400s 144.689us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 441.490s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 441.490s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 441.490s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 441.490s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.190s 620.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.400s 144.689us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.410s 2149.838us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.490s 2201.883us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 441.490s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.760s 18.041us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.820s 71.684us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.730s 21.347us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.910s 65.261us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.810s 47.014us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.800s 13.530us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.910s 20.052us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.800s 13.530us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.430s 230.291us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 37.550s 3408.401us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 63602677778480269147791728132331813715711228250214630165046188118422052363462 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 80753941850458135459898174251876787282656123805474004494296423251369621379765 88
UVM_INFO @ 13529640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---