Simulation Results: csrng

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.56 %
  • code
  • 94.81 %
  • assert
  • 95.41 %
  • func
  • 72.45 %
  • block
  • 97.05 %
  • line
  • 97.87 %
  • branch
  • 92.77 %
  • toggle
  • 93.37 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 81.521us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 44.820us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 20.167us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 5.000s 89.294us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 85.298us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 17.653us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 20.167us 1 1 100.00
csrng_csr_aliasing 4.000s 85.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 456.950us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 68.178us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 68.178us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 81.000s 1971.525us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 39.093us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 24.252us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 46.756us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 46.756us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 44.820us 1 1 100.00
csrng_csr_rw 2.000s 20.167us 1 1 100.00
csrng_csr_aliasing 4.000s 85.298us 1 1 100.00
csrng_same_csr_outstanding 2.000s 56.929us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 44.820us 1 1 100.00
csrng_csr_rw 2.000s 20.167us 1 1 100.00
csrng_csr_aliasing 4.000s 85.298us 1 1 100.00
csrng_same_csr_outstanding 2.000s 56.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
csrng_tl_intg_err 3.000s 196.865us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 11.177us 0 1 0.00
csrng_csr_rw 2.000s 20.167us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 456.950us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 81.000s 1971.525us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 456.950us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 81.000s 1971.525us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 456.950us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 196.865us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
csrng_sec_cm 2.000s 42.615us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 133.993us 1 1 100.00
csrng_err 2.000s 29.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 1.000s 12.182us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 70339154623466858204943598773172795768747827245936382030175132105305633595778 100
UVM_INFO @ 68177743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 113888084468503165694759270860345672887760206001290010522003323487348704984390 99
UVM_INFO @ 11177415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 67933474532625861504107377927120453344567328773047218807749089711730315312731 116
UVM_INFO @ 12182450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---