Simulation Results: edn/edn0

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.89 %
  • code
  • 79.04 %
  • assert
  • 95.88 %
  • func
  • 82.74 %
  • line
  • 96.90 %
  • branch
  • 89.40 %
  • cond
  • 85.61 %
  • toggle
  • 76.51 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 70.362us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 16.830us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 13.627us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.950s 1131.031us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.300s 41.826us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 99.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 13.627us 1 1 100.00
edn_csr_aliasing 1.300s 41.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.950s 76.497us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.950s 76.497us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.950s 76.497us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.970s 21.459us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.140s 60.584us 1 1 100.00
errs 1 1 100.00
edn_err 1.050s 28.424us 1 1 100.00
disable 2 2 100.00
edn_disable 0.900s 17.312us 1 1 100.00
edn_disable_auto_req_mode 1.040s 170.459us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.070s 307.605us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 101.156us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.840s 47.572us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.800s 156.210us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.800s 156.210us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 16.830us 1 1 100.00
edn_csr_rw 0.840s 13.627us 1 1 100.00
edn_csr_aliasing 1.300s 41.826us 1 1 100.00
edn_same_csr_outstanding 1.050s 42.481us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 16.830us 1 1 100.00
edn_csr_rw 0.840s 13.627us 1 1 100.00
edn_csr_aliasing 1.300s 41.826us 1 1 100.00
edn_same_csr_outstanding 1.050s 42.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.940s 637.407us 1 1 100.00
edn_tl_intg_err 1.460s 118.058us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 48.440us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.140s 60.584us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.940s 637.407us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.940s 637.407us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.940s 637.407us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.940s 637.407us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.140s 60.584us 1 1 100.00
edn_sec_cm 3.940s 637.407us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.140s 60.584us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.460s 118.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 53.240s 4557.826us 1 1 100.00