Simulation Results: edn/edn1

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.07 %
  • code
  • 83.45 %
  • assert
  • 97.92 %
  • func
  • 79.83 %
  • line
  • 97.88 %
  • branch
  • 92.42 %
  • cond
  • 88.54 %
  • toggle
  • 95.25 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 33.339us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 23.952us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.710s 177.815us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.500s 370.459us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.230s 67.482us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.160s 31.298us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.710s 177.815us 1 1 100.00
edn_csr_aliasing 1.230s 67.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.890s 81.680us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.890s 81.680us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.890s 81.680us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 22.165us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 50.314us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 28.131us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 48.051us 1 1 100.00
edn_disable_auto_req_mode 0.880s 31.472us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.100s 45.694us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.690s 44.886us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 48.689us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.360s 170.519us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.360s 170.519us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 23.952us 1 1 100.00
edn_csr_rw 0.710s 177.815us 1 1 100.00
edn_csr_aliasing 1.230s 67.482us 1 1 100.00
edn_same_csr_outstanding 0.950s 26.150us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 23.952us 1 1 100.00
edn_csr_rw 0.710s 177.815us 1 1 100.00
edn_csr_aliasing 1.230s 67.482us 1 1 100.00
edn_same_csr_outstanding 0.950s 26.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.220s 375.952us 1 1 100.00
edn_tl_intg_err 1.870s 92.196us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 20.189us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 50.314us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.220s 375.952us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.220s 375.952us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.220s 375.952us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.220s 375.952us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 50.314us 1 1 100.00
edn_sec_cm 2.220s 375.952us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 50.314us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.870s 92.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 18.270s 2036.780us 1 1 100.00