Simulation Results: entropy_src/rng_4bits

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.27 %
  • code
  • 88.23 %
  • assert
  • 84.07 %
  • func
  • 47.51 %
  • block
  • 94.30 %
  • line
  • 97.01 %
  • branch
  • 86.47 %
  • toggle
  • 76.72 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 67.690us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 26.511us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 16.651us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 411.156us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 208.766us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 71.300us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 16.651us 1 1 100.00
entropy_src_csr_aliasing 2.000s 208.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 67.690us 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
entropy_src_fw_ov 51.000s 13072.399us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 51.000s 13072.399us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 78.000s 13150.302us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
entropy_src_intr 9.000s 366.205us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
entropy_src_functional_alerts 4.000s 722.501us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 39.000s 14808.459us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 217.385us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 72.532us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 24.397us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 97.911us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 29.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 29.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 26.511us 1 1 100.00
entropy_src_csr_rw 1.000s 16.651us 1 1 100.00
entropy_src_csr_aliasing 2.000s 208.766us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 56.920us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 26.511us 1 1 100.00
entropy_src_csr_rw 1.000s 16.651us 1 1 100.00
entropy_src_csr_aliasing 2.000s 208.766us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 56.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 69.121us 1 1 100.00
entropy_src_tl_intg_err 2.000s 178.525us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
entropy_src_cfg_regwen 1.000s 15.011us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
entropy_src_fw_ov 51.000s 13072.399us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 217.385us 1 1 100.00
entropy_src_sec_cm 2.000s 69.121us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 217.385us 1 1 100.00
entropy_src_sec_cm 2.000s 69.121us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 121.000s 14039.892us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 217.385us 1 1 100.00
entropy_src_sec_cm 2.000s 69.121us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 217.385us 1 1 100.00
entropy_src_sec_cm 2.000s 69.121us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 217.385us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 722.501us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 178.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 54.000s 14101.268us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 4.000s 501.945us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 39762239103111412487024849348791663671358039408208747657525375244564415073869 318
UVM_INFO @ 501944721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 89902879539426370497465073484963503103280915963080026410972267623499158488369 113
UVM_INFO @ 71300334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---