Simulation Results: flash_ctrl

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 94.33 %
  • assert
  • 97.02 %
  • func
  • 96.04 %
  • line
  • 95.93 %
  • branch
  • 97.10 %
  • cond
  • 93.63 %
  • toggle
  • 97.23 %
  • FSM
  • 87.76 %
Validation stages
V1
100.00%
V2
98.28%
V2S
91.67%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 45.860s 37.462us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.560s 32.977us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.940s 158.518us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 58.310s 3623.756us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 30.060s 1752.018us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.100s 108.909us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
flash_ctrl_csr_aliasing 30.060s 1752.018us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.210s 31.198us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.820s 128.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.130s 121.036us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 23.230s 40.544us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1146.240s 84014.171us 1 1 100.00
flash_ctrl_hw_rma_reset 526.980s 50126.853us 1 1 100.00
flash_ctrl_lcmgr_intg 5.800s 23.261us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1404.360s 546022.573us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 211.080s 11276.832us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.330s 90.561us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1756.820s 207413.975us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 40.340s 93.952us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.910s 102.793us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.340s 31.236us 1 1 100.00
flash_ctrl_re_evict 17.650s 86.931us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 59.170s 389.885us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 59.170s 389.885us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 397.810s 12604.521us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.760s 553.583us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 167.660s 47.322us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 362.690s 4302.913us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 387.150s 1819.511us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 750.660s 882.828us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.010s 72.743us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 132.120s 1832.625us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.670s 18.771us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.520s 53.313us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 719.590s 738.825us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 120.490s 3064.359us 1 1 100.00
flash_ctrl_otp_reset 45.320s 139.656us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1146.240s 84014.171us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 126.960s 15526.664us 1 1 100.00
flash_ctrl_intr_wr 42.010s 3345.762us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 160.950s 25692.728us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 197.260s 111511.815us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 43.910s 5966.823us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.880s 1026.665us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 14.670s 30.504us 1 1 100.00
flash_ctrl_ro_derr 112.370s 1541.203us 1 1 100.00
flash_ctrl_rw_derr 113.580s 7843.135us 1 1 100.00
flash_ctrl_derr_detect 106.850s 1471.635us 1 1 100.00
flash_ctrl_integrity 355.130s 17751.266us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.640s 79.412us 1 1 100.00
flash_ctrl_ro_serr 116.050s 846.936us 1 1 100.00
flash_ctrl_rw_serr 136.370s 6795.200us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 35.460s 1160.402us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 37.790s 1782.669us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 130.360s 12030.259us 1 1 100.00
flash_ctrl_write_word_sweep 6.940s 163.906us 1 1 100.00
flash_ctrl_read_word_sweep 6.700s 28.962us 1 1 100.00
flash_ctrl_ro 83.440s 2325.058us 1 1 100.00
flash_ctrl_rw 35.780s 718.686us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.570s 1400.451us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 605.740s 123095.538us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 35.190s 10035.193us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.830s 39.699us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.590s 51.840us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.840s 324.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.840s 324.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.940s 158.518us 1 1 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
flash_ctrl_csr_aliasing 30.060s 1752.018us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.740s 101.859us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.940s 158.518us 1 1 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
flash_ctrl_csr_aliasing 30.060s 1752.018us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.740s 101.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 10.000s 213.785us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
flash_ctrl_tl_intg_err 307.630s 1436.929us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 307.630s 1436.929us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 307.630s 1436.929us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.480s 384.563us 1 1 100.00
flash_ctrl_wr_intg 6.920s 89.114us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 45.860s 37.462us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 45.320s 139.656us 1 1 100.00
flash_ctrl_disable 10.670s 18.771us 1 1 100.00
flash_ctrl_sec_info_access 31.820s 478.095us 1 1 100.00
flash_ctrl_connect 7.520s 53.313us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.140s 79.995us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.010s 129.646us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.140s 85.650us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.670s 18.771us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.480s 384.563us 1 1 100.00
flash_ctrl_access_after_disable 6.070s 39.537us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.760s 28.394us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.670s 18.771us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.760s 553.583us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 35.780s 718.686us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 136.370s 6795.200us 1 1 100.00
flash_ctrl_rw_derr 113.580s 7843.135us 1 1 100.00
flash_ctrl_integrity 355.130s 17751.266us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1146.240s 84014.171us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.060s 890.016us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.310s 72.560us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 0 1 0.00
flash_ctrl_phy_ack_consistency 6.390s 20.992us 0 1 0.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1704.260s 1458.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.020s 123.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 122.260s 791.718us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 1 test run
flash_ctrl_rw 53955012805015866124470488364022055275338194989831946647588106838662296779377 108
UVM_INFO @ 718685.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) 1 test run
flash_ctrl_phy_ack_consistency 56986963125749318073817396549003639998486783093739199446158323211352146724557 109
UVM_INFO @ 20992.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---