Simulation Results: hmac

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.89 %
  • code
  • 97.69 %
  • assert
  • 97.60 %
  • func
  • 44.39 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.300s 3878.055us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.940s 58.297us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.990s 61.035us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.070s 345.557us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.450s 344.889us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 52.740s 11669.184us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.990s 61.035us 1 1 100.00
hmac_csr_aliasing 2.450s 344.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 34.590s 1171.580us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 13.900s 1557.584us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.570s 725.972us 1 1 100.00
hmac_test_sha384_vectors 337.470s 27311.988us 1 1 100.00
hmac_test_sha512_vectors 21.230s 1484.698us 1 1 100.00
hmac_test_hmac256_vectors 7.600s 867.798us 1 1 100.00
hmac_test_hmac384_vectors 10.580s 417.550us 1 1 100.00
hmac_test_hmac512_vectors 8.920s 621.239us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.160s 555.523us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 697.430s 14724.226us 1 1 100.00
error 1 1 100.00
hmac_error 44.400s 85661.279us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 38.690s 14178.713us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.300s 3878.055us 1 1 100.00
hmac_long_msg 34.590s 1171.580us 1 1 100.00
hmac_back_pressure 13.900s 1557.584us 1 1 100.00
hmac_datapath_stress 697.430s 14724.226us 1 1 100.00
hmac_burst_wr 5.160s 555.523us 1 1 100.00
hmac_stress_all 7.270s 305.742us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.300s 3878.055us 1 1 100.00
hmac_long_msg 34.590s 1171.580us 1 1 100.00
hmac_back_pressure 13.900s 1557.584us 1 1 100.00
hmac_datapath_stress 697.430s 14724.226us 1 1 100.00
hmac_wipe_secret 38.690s 14178.713us 1 1 100.00
hmac_test_sha256_vectors 8.570s 725.972us 1 1 100.00
hmac_test_sha384_vectors 337.470s 27311.988us 1 1 100.00
hmac_test_sha512_vectors 21.230s 1484.698us 1 1 100.00
hmac_test_hmac256_vectors 7.600s 867.798us 1 1 100.00
hmac_test_hmac384_vectors 10.580s 417.550us 1 1 100.00
hmac_test_hmac512_vectors 8.920s 621.239us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.300s 3878.055us 1 1 100.00
hmac_long_msg 34.590s 1171.580us 1 1 100.00
hmac_back_pressure 13.900s 1557.584us 1 1 100.00
hmac_datapath_stress 697.430s 14724.226us 1 1 100.00
hmac_burst_wr 5.160s 555.523us 1 1 100.00
hmac_error 44.400s 85661.279us 1 1 100.00
hmac_wipe_secret 38.690s 14178.713us 1 1 100.00
hmac_test_sha256_vectors 8.570s 725.972us 1 1 100.00
hmac_test_sha384_vectors 337.470s 27311.988us 1 1 100.00
hmac_test_sha512_vectors 21.230s 1484.698us 1 1 100.00
hmac_test_hmac256_vectors 7.600s 867.798us 1 1 100.00
hmac_test_hmac384_vectors 10.580s 417.550us 1 1 100.00
hmac_test_hmac512_vectors 8.920s 621.239us 1 1 100.00
hmac_stress_all 7.270s 305.742us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 7.270s 305.742us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 19.154us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 128.392us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.790s 182.167us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.790s 182.167us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.940s 58.297us 1 1 100.00
hmac_csr_rw 0.990s 61.035us 1 1 100.00
hmac_csr_aliasing 2.450s 344.889us 1 1 100.00
hmac_same_csr_outstanding 1.120s 108.666us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.940s 58.297us 1 1 100.00
hmac_csr_rw 0.990s 61.035us 1 1 100.00
hmac_csr_aliasing 2.450s 344.889us 1 1 100.00
hmac_same_csr_outstanding 1.120s 108.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.030s 66.449us 1 1 100.00
hmac_tl_intg_err 2.450s 184.368us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.450s 184.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.300s 3878.055us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.530s 322.066us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 393.070s 8837.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.260s 102.638us 1 1 100.00