Simulation Results

Simulation Results: i2c

29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.65 %

code
82.50 %

assert
97.04 %

func
83.40 %

line
96.69 %

branch
93.04 %

cond
87.86 %

toggle
89.66 %

FSM
45.24 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	10.280s	5851.952us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.540s	1179.800us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.890s	30.771us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.810s	202.321us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.260s	1235.612us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.780s	117.102us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.020s	126.533us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.810s	202.321us	1	1	100.00
	i2c_csr_aliasing	1.780s	117.102us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.300s	100.164us	1	1	100.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	392.660s	160003.487us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	7.160s	8680.488us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.930s	23.631us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	33.640s	18921.378us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	46.750s	1389.711us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.040s	116.170us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.260s	3347.283us	1	1	100.00
	i2c_host_fifo_reset_rx	2.770s	186.048us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	84.470s	10182.578us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.160s	7047.717us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.720s	63.322us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.830s	1911.966us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	110.470s	16109.744us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.600s	3984.708us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	48.230s	1812.929us	1	1	100.00
	i2c_target_intr_smoke	3.160s	3812.288us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.160s	2047.632us	1	1	100.00
	i2c_target_fifo_reset_tx	0.860s	402.102us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	34.560s	37925.815us	1	1	100.00
	i2c_target_stress_rd	48.230s	1812.929us	1	1	100.00
	i2c_target_intr_stress_wr	9.790s	4626.122us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.010s	5172.875us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	8.270s	3855.362us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.380s	2738.680us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.140s	1345.752us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.800s	881.776us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.830s	99.041us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	7.160s	8680.488us	1	1	100.00
	i2c_host_perf_precise	1.390s	42.028us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.160s	7047.717us	1	1	100.00
target_mode_tx_stretch_ctrl				0	1	0.00
	i2c_target_tx_stretch_ctrl	0.760s	5.457us	0	1	0.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.140s	5395.223us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.730s	507.969us	1	1	100.00
	i2c_target_nack_txstretch	1.630s	485.900us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.670s	259.779us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.630s	1996.480us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.790s	22.784us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.840s	18.234us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	245.839us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	245.839us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.890s	30.771us	1	1	100.00
	i2c_csr_rw	0.810s	202.321us	1	1	100.00
	i2c_csr_aliasing	1.780s	117.102us	1	1	100.00
	i2c_same_csr_outstanding	0.780s	22.647us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.890s	30.771us	1	1	100.00
	i2c_csr_rw	0.810s	202.321us	1	1	100.00
	i2c_csr_aliasing	1.780s	117.102us	1	1	100.00
	i2c_same_csr_outstanding	0.780s	22.647us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.800s	1214.496us	1	1	100.00
	i2c_sec_cm	1.130s	66.132us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.800s	1214.496us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.280s	11896.969us	1
target_error_intr				1
	i2c_target_unexp_stop	0.810s	354.777us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.750s	1252.247us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	83669011211141288127458426251404032048203706547990554518165042092342189400829	90	UVM_INFO @ 11896968921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	47303228857998931318356255313995766257500277406861884011846095715835227490215	86	UVM_INFO @ 1252246859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	111393471713573155849973496274212402142000266849233025735581339964905803056619	84	UVM_INFO @ 1911965764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	29582545061675491563747296255196281953441958404615039379595795174988853950364	78	UVM_INFO @ 354776756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	60004938520322416429197060639517546450453218241803380467034927381974528262288	79	UVM_INFO @ 63321508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure				1 test run
	i2c_target_tx_stretch_ctrl	21048055544912680758070036779509178658752097291039278645895725971137941999590	124	src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.