Simulation Results: keymgr

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.51 %
  • code
  • 94.80 %
  • assert
  • 97.72 %
  • func
  • 64.02 %
  • line
  • 98.76 %
  • branch
  • 96.26 %
  • cond
  • 92.00 %
  • toggle
  • 96.26 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.650s 106.225us 1 1 100.00
random 1 1 100.00
keymgr_random 3.320s 154.760us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.400s 42.706us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.640s 1550.445us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 12.000s 942.923us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.860s 32.323us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
keymgr_csr_aliasing 12.000s 942.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 6.450s 218.879us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.360s 525.265us 1 1 100.00
keymgr_sideload_kmac 3.120s 349.065us 1 1 100.00
keymgr_sideload_aes 3.270s 379.145us 1 1 100.00
keymgr_sideload_otbn 2.280s 56.094us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.900s 36.243us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 4.840s 602.279us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.710s 90.833us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.520s 200.741us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 4.370s 2879.212us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.190s 659.283us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 16.980s 2984.721us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.860s 97.659us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.920s 59.436us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.570s 161.130us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.570s 161.130us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.400s 42.706us 1 1 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
keymgr_csr_aliasing 12.000s 942.923us 1 1 100.00
keymgr_same_csr_outstanding 1.280s 74.035us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.400s 42.706us 1 1 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
keymgr_csr_aliasing 12.000s 942.923us 1 1 100.00
keymgr_same_csr_outstanding 1.280s 74.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
keymgr_tl_intg_err 3.180s 125.927us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.220s 158.787us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.220s 158.787us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.220s 158.787us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.220s 158.787us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 7.530s 491.561us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.180s 125.927us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.220s 158.787us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 6.450s 218.879us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.320s 154.760us 1 1 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.320s 154.760us 1 1 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.320s 154.760us 1 1 100.00
keymgr_csr_rw 1.360s 26.503us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 4.840s 602.279us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.370s 2879.212us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.370s 2879.212us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.320s 154.760us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.310s 270.624us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.990s 198.159us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 4.840s 602.279us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.990s 198.159us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.990s 198.159us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.990s 198.159us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.160s 402.498us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.990s 198.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.400s 179.778us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 75480422791807067439256704646061958361587803189484589163276604421597335034490 470
UVM_INFO @ 179778256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---