Simulation Results: kmac/masked

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.50 %
  • code
  • 69.71 %
  • assert
  • 96.91 %
  • func
  • 77.87 %
  • line
  • 96.14 %
  • branch
  • 90.31 %
  • cond
  • 86.36 %
  • toggle
  • 29.56 %
  • FSM
  • 46.20 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 69.600s 21631.742us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.930s 30.341us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.890s 24.553us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 18.550s 7490.762us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.450s 2174.660us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.420s 367.326us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.890s 24.553us 1 1 100.00
kmac_csr_aliasing 5.450s 2174.660us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.710s 36.864us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.040s 107.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 3536.430s 127884.408us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 711.500s 94507.615us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 34.250s 3078.740us 1 1 100.00
kmac_test_vectors_sha3_256 2270.090s 185425.944us 1 1 100.00
kmac_test_vectors_sha3_384 26.900s 5796.460us 1 1 100.00
kmac_test_vectors_sha3_512 15.460s 3458.328us 1 1 100.00
kmac_test_vectors_shake_128 166.510s 11737.508us 1 1 100.00
kmac_test_vectors_shake_256 352.640s 28552.243us 1 1 100.00
kmac_test_vectors_kmac 2.470s 190.006us 1 1 100.00
kmac_test_vectors_kmac_xof 2.890s 356.969us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 15.070s 3331.745us 1 1 100.00
app 0 1 0.00
kmac_app 6.310s 1329.983us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.530s 132.895us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 9.520s 1212.905us 0 1 0.00
error 0 1 0.00
kmac_error 5.220s 169.581us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.170s 48.147us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.960s 9.548us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 32.020s 8058.222us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.970s 192.544us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.320s 60.379us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.290s 85.790us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 21.400s 457.450us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.740s 35.586us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.830s 102.745us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.520s 1410.017us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.520s 1410.017us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.930s 30.341us 1 1 100.00
kmac_csr_rw 0.890s 24.553us 1 1 100.00
kmac_csr_aliasing 5.450s 2174.660us 1 1 100.00
kmac_same_csr_outstanding 1.690s 76.876us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.930s 30.341us 1 1 100.00
kmac_csr_rw 0.890s 24.553us 1 1 100.00
kmac_csr_aliasing 5.450s 2174.660us 1 1 100.00
kmac_same_csr_outstanding 1.690s 76.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.250s 52.626us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.250s 52.626us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.250s 52.626us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.250s 52.626us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.990s 95.124us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 84.610s 9141.684us 1 1 100.00
kmac_tl_intg_err 2.380s 468.580us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.380s 468.580us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.290s 85.790us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 69.600s 21631.742us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 15.070s 3331.745us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.250s 52.626us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 84.610s 9141.684us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 84.610s 9141.684us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 84.610s 9141.684us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 69.600s 21631.742us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.290s 85.790us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 84.610s 9141.684us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 4.560s 327.504us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 69.600s 21631.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 5.520s 226.015us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 5 test runs
kmac_app 13064366716398751009201662782194034034649617115045103143501724241466192447592 80
UVM_INFO @ 1329983375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 67629827104843449313353540233134942312685016262079922670844621580522647246635 77
UVM_INFO @ 132894601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 68006756907923461694401570774633830735038253956846316455444659888592999936144 82
UVM_INFO @ 1212904854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 107694774831028238681833758185505384535448348872872264041992507991124998676613 81
UVM_INFO @ 169581133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 28355565671083822323691099590496310270378944203218471918240841902380880502371 96
UVM_INFO @ 226014831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 3 test runs
kmac_sideload_invalid 8048543420248891436396002379719856751221285905473879317757586155543997348546 79
UVM_ERROR @ 9548385 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 9548385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 44022148529660710586543297573103155343851430611487592186711297661998820895957 78
UVM_ERROR @ 48147495 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 48147495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 9513491424211836289352059582431700284657052294529176819467699845443196248027 78
UVM_ERROR @ 60378500 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 60378500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 70961777655085974066419588291129789458577860942994459528355377401924895202208 79
UVM_INFO @ 327503789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 47786959314433472236961953968094846373434892591914595536906120786037962474262 92
UVM_INFO @ 457449795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---