Simulation Results: kmac/unmasked

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.85 %
  • code
  • 66.23 %
  • assert
  • 96.50 %
  • func
  • 73.82 %
  • line
  • 92.84 %
  • branch
  • 87.13 %
  • cond
  • 83.74 %
  • toggle
  • 27.28 %
  • FSM
  • 40.15 %
Validation stages
V1
100.00%
V2
68.97%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 32.590s 6733.042us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.970s 59.470us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.030s 81.906us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 15.940s 6486.741us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 2.900s 144.737us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.170s 164.614us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.030s 81.906us 1 1 100.00
kmac_csr_aliasing 2.900s 144.737us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.700s 12.647us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.670s 43.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1130.220s 20935.743us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 200.580s 38160.011us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2373.660s 241457.312us 1 1 100.00
kmac_test_vectors_sha3_256 2061.920s 209746.683us 1 1 100.00
kmac_test_vectors_sha3_384 18.870s 1110.620us 1 1 100.00
kmac_test_vectors_sha3_512 15.890s 2581.102us 1 1 100.00
kmac_test_vectors_shake_128 135.070s 4856.736us 1 1 100.00
kmac_test_vectors_shake_256 100.670s 7564.641us 1 1 100.00
kmac_test_vectors_kmac 1.750s 331.243us 1 1 100.00
kmac_test_vectors_kmac_xof 2.130s 154.363us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 197.760s 35582.348us 1 1 100.00
app 0 1 0.00
kmac_app 0.990s 103.678us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 0.930s 10.913us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 1.200s 536.491us 0 1 0.00
error 0 1 0.00
kmac_error 24.400s 1614.445us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 0.870s 10.684us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.960s 18.978us 0 1 0.00
edn_timeout_error 0 1 0.00
kmac_edn_timeout_error 6.370s 1320.624us 0 1 0.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 12.910s 3261.811us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.060s 43.589us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.360s 50.651us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 1.180s 464.576us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.740s 24.611us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.810s 22.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.710s 32.261us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.710s 32.261us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.970s 59.470us 1 1 100.00
kmac_csr_rw 1.030s 81.906us 1 1 100.00
kmac_csr_aliasing 2.900s 144.737us 1 1 100.00
kmac_same_csr_outstanding 2.760s 786.096us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.970s 59.470us 1 1 100.00
kmac_csr_rw 1.030s 81.906us 1 1 100.00
kmac_csr_aliasing 2.900s 144.737us 1 1 100.00
kmac_same_csr_outstanding 2.760s 786.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.130s 72.513us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.130s 72.513us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.130s 72.513us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.130s 72.513us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.700s 1595.747us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 18.450s 3535.713us 1 1 100.00
kmac_tl_intg_err 3.200s 110.213us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.200s 110.213us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.360s 50.651us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 32.590s 6733.042us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 197.760s 35582.348us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.130s 72.513us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 18.450s 3535.713us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 18.450s 3535.713us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 18.450s 3535.713us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 32.590s 6733.042us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.360s 50.651us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 18.450s 3535.713us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 0.970s 85.936us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 32.590s 6733.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 47.510s 18704.328us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_app 111805451354971189137355017930739125052444020493535617697098079740919677344990 77
UVM_INFO @ 103677824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 74821858460017983586690880973838861082471465575018955069921940072445053913029 77
UVM_INFO @ 10913162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 104187116313112304511822672948405024855116529055419242552230101126142345056693 77
UVM_INFO @ 536491239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 34232526148840070841297636477005520646862378701374695887797777559996365434122 90
UVM_INFO @ 1614445321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 24141090629018234726884372181970096296665303425593662231450705194941671378335 77
UVM_INFO @ 43589445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 105949013478335012670804667523829639441875077005451716669576498343882049784862 79
UVM_INFO @ 464575878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 3 test runs
kmac_sideload_invalid 8572680965402534479633373175182205650813070344955346946697104889477775135188 79
UVM_ERROR @ 18977532 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 18977532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 28578169886781116908155604678313658839473493837068492265448591319104423956130 78
UVM_ERROR @ 10683900 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 10683900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_edn_timeout_error 98659340794227099558016158238315886249395557923405405007743920333733541405046 81
UVM_ERROR @ 1320623799 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 1320623799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 3660898530645238945001060555842347231406671199768768728174330575301181723779 77
UVM_INFO @ 85935606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 86718360410822537709086732672525548767072492126255912950090897370829551957763 165
UVM_INFO @ 18704328387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---