Simulation Results: lc_ctrl/volatile_unlock_disabled

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.48 %
  • code
  • 83.82 %
  • assert
  • 94.55 %
  • func
  • 93.06 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 78.94 %
  • toggle
  • 86.63 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 140.075us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.200s 16.573us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.770s 56.130us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.130s 513.128us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 83.739us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.120s 134.557us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.770s 56.130us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 83.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.970s 398.731us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.300s 273.776us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 13.832us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.130s 443.577us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.340s 831.974us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_prog_failure 2.130s 443.577us 1 1 100.00
lc_ctrl_errors 7.340s 831.974us 1 1 100.00
lc_ctrl_security_escalation 10.120s 767.576us 1 1 100.00
lc_ctrl_jtag_state_failure 30.860s 32201.099us 1 1 100.00
lc_ctrl_jtag_prog_failure 14.380s 10687.619us 1 1 100.00
lc_ctrl_jtag_errors 36.770s 8276.818us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.220s 921.809us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.980s 1411.718us 1 1 100.00
lc_ctrl_jtag_prog_failure 14.380s 10687.619us 1 1 100.00
lc_ctrl_jtag_errors 36.770s 8276.818us 1 1 100.00
lc_ctrl_jtag_access 1.610s 465.206us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.090s 1063.941us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.810s 276.524us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.380s 102.693us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.600s 1163.364us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.820s 432.967us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 63.432us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.100s 195.014us 1 1 100.00
lc_ctrl_jtag_alert_test 1.070s 235.866us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.110s 50.922us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.080s 101.388us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 25.460s 5311.780us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 65.764us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.610s 26.529us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.610s 26.529us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.200s 16.573us 1 1 100.00
lc_ctrl_csr_rw 0.770s 56.130us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 83.739us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.100s 52.988us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.200s 16.573us 1 1 100.00
lc_ctrl_csr_rw 0.770s 56.130us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 83.739us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.100s 52.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
lc_ctrl_tl_intg_err 1.910s 342.552us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.910s 342.552us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.300s 273.776us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.980s 244.987us 1 1 100.00
lc_ctrl_sec_cm 5.560s 250.597us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 10.120s 767.576us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.970s 398.731us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.980s 1411.718us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.310s 997.996us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.310s 997.996us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.650s 5625.855us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.770s 1378.335us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.770s 1378.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 16.590s 3396.577us 1 1 100.00