Simulation Results: lc_ctrl/volatile_unlock_enabled

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.03 %
  • code
  • 83.08 %
  • assert
  • 94.13 %
  • func
  • 92.88 %
  • line
  • 97.09 %
  • branch
  • 93.37 %
  • cond
  • 79.06 %
  • toggle
  • 84.22 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.650s 51.421us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 29.613us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 40.590us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.830s 99.171us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 16.619us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.330s 50.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 40.590us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 16.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.270s 72.048us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.950s 280.623us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.730s 42.391us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.410s 431.467us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.050s 1504.481us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_prog_failure 2.410s 431.467us 1 1 100.00
lc_ctrl_errors 8.050s 1504.481us 1 1 100.00
lc_ctrl_security_escalation 6.100s 4984.715us 1 1 100.00
lc_ctrl_jtag_state_failure 18.470s 1303.632us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.620s 525.230us 1 1 100.00
lc_ctrl_jtag_errors 19.890s 4781.735us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.290s 715.073us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.990s 957.090us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.620s 525.230us 1 1 100.00
lc_ctrl_jtag_errors 19.890s 4781.735us 1 1 100.00
lc_ctrl_jtag_access 5.730s 2317.445us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.340s 2037.078us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.240s 320.477us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.030s 318.109us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.120s 671.856us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 11.870s 2698.202us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.550s 118.159us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.720s 362.056us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 322.514us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.950s 220.608us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.060s 17.225us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 76.160s 16701.066us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.040s 17.502us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.880s 629.828us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.880s 629.828us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 29.613us 1 1 100.00
lc_ctrl_csr_rw 0.830s 40.590us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 16.619us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 81.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 29.613us 1 1 100.00
lc_ctrl_csr_rw 0.830s 40.590us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 16.619us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 81.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
lc_ctrl_tl_intg_err 1.350s 122.815us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.350s 122.815us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.950s 280.623us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.440s 912.915us 1 1 100.00
lc_ctrl_sec_cm 9.420s 2198.591us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.100s 4984.715us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.270s 72.048us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.990s 957.090us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.860s 1451.581us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.860s 1451.581us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 15.550s 1752.006us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.680s 2507.409us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.680s 2507.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 21.400s 938.031us 1 1 100.00