Simulation Results: otbn

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.87 %
  • code
  • 81.00 %
  • assert
  • 87.68 %
  • func
  • 94.92 %
  • block
  • 97.66 %
  • line
  • 97.86 %
  • branch
  • 81.57 %
  • toggle
  • 81.18 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 202.274us 1 1 100.00
single_binary 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 35.000s 15.400us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 34.000s 22.490us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 36.000s 48.761us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 34.000s 58.170us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 127.758us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 34.000s 22.490us 1 1 100.00
otbn_csr_aliasing 34.000s 58.170us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 77.000s 3369.193us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 53.000s 2449.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 41.000s 1362.646us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 51.000s 891.050us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 49.000s 121.670us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 47.000s 190.364us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 43.000s 72.089us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 24.674us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 26.663us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 36.000s 21.563us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 30.000s 49.344us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 454.880us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 454.880us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 35.000s 15.400us 1 1 100.00
otbn_csr_rw 34.000s 22.490us 1 1 100.00
otbn_csr_aliasing 34.000s 58.170us 1 1 100.00
otbn_same_csr_outstanding 6.000s 127.751us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 35.000s 15.400us 1 1 100.00
otbn_csr_rw 34.000s 22.490us 1 1 100.00
otbn_csr_aliasing 34.000s 58.170us 1 1 100.00
otbn_same_csr_outstanding 6.000s 127.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 41.000s 31.646us 1 1 100.00
otbn_dmem_err 37.000s 28.030us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 41.000s 21.591us 1 1 100.00
otbn_controller_ispr_rdata_err 39.000s 204.039us 1 1 100.00
otbn_mac_bignum_acc_err 32.000s 100.867us 1 1 100.00
otbn_urnd_err 8.000s 24.142us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 30.000s 17.221us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 29.000s 22.809us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 27.650us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
otbn_tl_intg_err 39.000s 286.825us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 27.000s 372.466us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 202.274us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 37.000s 28.030us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 41.000s 31.646us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 39.000s 286.825us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 43.000s 72.089us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 41.000s 31.646us 1 1 100.00
otbn_dmem_err 37.000s 28.030us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 24.674us 1 1 100.00
otbn_illegal_mem_acc 30.000s 17.221us 1 1 100.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 41.000s 31.646us 1 1 100.00
otbn_dmem_err 37.000s 28.030us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 24.674us 1 1 100.00
otbn_illegal_mem_acc 30.000s 17.221us 1 1 100.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 43.000s 72.089us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 41.000s 31.646us 1 1 100.00
otbn_dmem_err 37.000s 28.030us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 24.674us 1 1 100.00
otbn_illegal_mem_acc 30.000s 17.221us 1 1 100.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 34.000s 28.158us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 25.026us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 28.000s 132.271us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 28.000s 132.271us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 17.004us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 582.866us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 27.034us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 27.034us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 25.686us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 49.000s 121.670us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 14.000s 37.611us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 18.000s 40.398us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 22.000s 149.202us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 258.000s 1072.004us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 92.754us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 54478851280589658504345649048673236191403975149304020076941706274263389719352 260
UVM_INFO @ 1072004316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 14605605266884337911324739498163475082562827514594387813379966911056375150309 137
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 149201721 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 149201721 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 149201721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---