Simulation Results: pwrmgr

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.32 %
  • code
  • 92.99 %
  • assert
  • 97.13 %
  • func
  • 98.85 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 96.04 %
  • toggle
  • 99.62 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 104.576us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.960s 42.635us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.730s 16.187us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.880s 182.441us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.930s 69.967us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.000s 77.960us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.730s 16.187us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 69.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.880s 145.503us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.880s 145.503us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.620s 125.527us 1 1 100.00
pwrmgr_lowpower_invalid 0.700s 43.796us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.700s 49.543us 1 1 100.00
pwrmgr_reset_invalid 0.640s 64.030us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.700s 49.543us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.650s 66.945us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.760s 117.731us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.110s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.070s 851.800us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 165.528us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.960s 240.083us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.960s 240.083us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.960s 42.635us 1 1 100.00
pwrmgr_csr_rw 0.730s 16.187us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 69.967us 1 1 100.00
pwrmgr_same_csr_outstanding 0.950s 46.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.960s 42.635us 1 1 100.00
pwrmgr_csr_rw 0.730s 16.187us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 69.967us 1 1 100.00
pwrmgr_same_csr_outstanding 0.950s 46.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.270s 470.939us 1 1 100.00
pwrmgr_sec_cm 1.230s 314.968us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.230s 314.968us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.230s 314.968us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.270s 470.939us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.720s 815.391us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.650s 66.945us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.140s 809.317us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.760s 58.312us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 34.925us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.230s 314.968us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.230s 314.968us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.230s 314.968us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.600s 29.591us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.590s 53.846us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 322.186us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 16.187us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 16.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.840s 102.046us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.320s 8900.024us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 115539347460557046207652100031743074503709452675558547097607115990811564036141 79
UVM_ERROR @ 102045600 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102045600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 54504382094476464687083292057421104303181006613473647068707385555700578777843 80
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks 1 test run
pwrmgr_reset_invalid 101286533669570395662124831994980425045247670698302363766452943707220911734082 88
UVM_INFO @ 64029888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---