Simulation Results: rom_ctrl/64kb

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.86 %
  • code
  • 97.01 %
  • assert
  • 97.39 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 95.52 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.630s 395.588us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.790s 709.402us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.360s 212.386us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.180s 207.473us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.580s 542.641us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.050s 215.687us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.360s 212.386us 1 1 100.00
rom_ctrl_csr_aliasing 6.580s 542.641us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.470s 539.838us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.920s 297.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 9.470s 988.450us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 22.500s 6932.073us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.020s 1369.565us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.500s 1216.625us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.120s 698.306us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.120s 698.306us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.790s 709.402us 1 1 100.00
rom_ctrl_csr_rw 6.360s 212.386us 1 1 100.00
rom_ctrl_csr_aliasing 6.580s 542.641us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.190s 301.327us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.790s 709.402us 1 1 100.00
rom_ctrl_csr_rw 6.360s 212.386us 1 1 100.00
rom_ctrl_csr_aliasing 6.580s 542.641us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.190s 301.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.840s 3727.346us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 463.480s 668.177us 1 1 100.00
rom_ctrl_tl_intg_err 100.880s 2623.865us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 463.480s 668.177us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 463.480s 668.177us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 463.480s 668.177us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 463.480s 668.177us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.630s 395.588us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.630s 395.588us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.630s 395.588us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 100.880s 2623.865us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
rom_ctrl_kmac_err_chk 12.020s 1369.565us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.980s 8154.794us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.840s 3727.346us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 463.480s 668.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 246.640s 15721.461us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 115092706169396775282720706274784062849016401603074907679660182571129618943437 79
UVM_INFO @ 988449603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---