Simulation Results: rstmgr

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 99.23 %
  • assert
  • 98.53 %
  • func
  • 95.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.61 %
  • toggle
  • 98.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.390s 298.781us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.020s 144.947us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.920s 88.322us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.680s 698.953us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.730s 229.944us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.860s 109.124us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.920s 88.322us 1 1 100.00
rstmgr_csr_aliasing 1.730s 229.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.310s 212.940us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.400s 161.982us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.850s 94.871us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.130s 1878.755us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.130s 1878.755us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.130s 1878.755us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.130s 1878.755us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 2.930s 908.500us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.780s 76.447us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.880s 533.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.880s 533.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.020s 144.947us 1 1 100.00
rstmgr_csr_rw 0.920s 88.322us 1 1 100.00
rstmgr_csr_aliasing 1.730s 229.944us 1 1 100.00
rstmgr_same_csr_outstanding 1.130s 151.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.020s 144.947us 1 1 100.00
rstmgr_csr_rw 0.920s 88.322us 1 1 100.00
rstmgr_csr_aliasing 1.730s 229.944us 1 1 100.00
rstmgr_same_csr_outstanding 1.130s 151.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 23.530s 16825.002us 1 1 100.00
rstmgr_tl_intg_err 2.140s 491.944us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 23.530s 16825.002us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 23.530s 16825.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.140s 491.944us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.990s 186.573us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.430s 2812.021us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.010s 301.529us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 23.530s 16825.002us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 88.322us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 88.322us 1 1 100.00