Simulation Results: rv_timer

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.71 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 92.65 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.690s 55.110us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.670s 119.050us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.740s 66.948us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.840s 9981.314us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.840s 131.150us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.600s 68.541us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.740s 66.948us 1 1 100.00
rv_timer_csr_aliasing 0.840s 131.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 6.130s 11804.722us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.320s 3467.901us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 8.170s 12955.196us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 8.170s 12955.196us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.200s 14936.838us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 21.592us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.540s 77.177us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.140s 239.071us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.140s 239.071us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 119.050us 1 1 100.00
rv_timer_csr_rw 0.740s 66.948us 1 1 100.00
rv_timer_csr_aliasing 0.840s 131.150us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 36.847us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 119.050us 1 1 100.00
rv_timer_csr_rw 0.740s 66.948us 1 1 100.00
rv_timer_csr_aliasing 0.840s 131.150us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 36.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.720s 36.571us 1 1 100.00
rv_timer_tl_intg_err 1.070s 314.957us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.070s 314.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.610s 22.476us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.330s 796.963us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 5.560s 1269.580us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 78658261884555726091715451472374911540049643953740254099339059641707650871525 75
UVM_INFO @ 796963211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 13554773292647414331330251123337525114374146920143963183619852225995636897100 75
UVM_INFO @ 11804721846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---