Simulation Results: spi_host

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.27 %
  • code
  • 91.30 %
  • assert
  • 96.03 %
  • func
  • 89.50 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 46.000s 1999.393us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 38.646us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 225.308us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 78.978us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 102.897us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 45.773us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 225.308us 1 1 100.00
spi_host_csr_aliasing 2.000s 102.897us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 116.556us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 99.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 25.992us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 30.000s 1375.275us 1 1 100.00
spi_host_error_cmd 1.000s 19.131us 1 1 100.00
spi_host_event 19.000s 3409.056us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 79.121us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 79.121us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 79.121us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 385.000s 52850.935us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 422.816us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 40.807us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 79.121us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 79.121us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 46.000s 1999.393us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 46.000s 1999.393us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 8.000s 616.344us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 626.415us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 30.000s 3166.854us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 256.373us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 30.000s 1375.275us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 35.857us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 20.283us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 176.438us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 176.438us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 38.646us 1 1 100.00
spi_host_csr_rw 1.000s 225.308us 1 1 100.00
spi_host_csr_aliasing 2.000s 102.897us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 31.880us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 38.646us 1 1 100.00
spi_host_csr_rw 1.000s 225.308us 1 1 100.00
spi_host_csr_aliasing 2.000s 102.897us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 31.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 138.429us 1 1 100.00
spi_host_sec_cm 1.000s 1047.321us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 138.429us 1 1 100.00