Simulation Results: sram_ctrl/main

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.52 %
  • code
  • 94.95 %
  • assert
  • 97.41 %
  • func
  • 94.20 %
  • block
  • 95.09 %
  • line
  • 95.72 %
  • branch
  • 92.23 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 3030.674us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 65.520us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 110.873us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 91.246us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.907us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 2018.790us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 110.873us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.907us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 115.000s 13409.112us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 76.000s 6697.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 36.000s 16590.069us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 113.000s 14583.813us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 121.000s 25117.554us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 45.000s 12221.693us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 17627.225us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 25.000s 6699.048us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 745.656us 1 1 100.00
sram_ctrl_partial_access_b2b 245.000s 21577.436us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 6.000s 2867.015us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 696.282us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 677.548us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 12139.479us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1473.245us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 37.000s 43280.077us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 37.470us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 126.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 126.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 65.520us 1 1 100.00
sram_ctrl_csr_rw 1.000s 110.873us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.907us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 29.911us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 65.520us 1 1 100.00
sram_ctrl_csr_rw 1.000s 110.873us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.907us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 29.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 10102.030us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1072.482us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 154.100us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1072.482us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 154.100us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 12139.479us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 12139.479us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 110.873us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 25.000s 6699.048us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 6699.048us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 6699.048us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 17627.225us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 689.903us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 10102.030us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 1359.976us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 3030.674us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 3030.674us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 25.000s 6699.048us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1072.482us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 17627.225us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1072.482us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1072.482us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 3030.674us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1072.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 22.000s 1325.583us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 70972616151362023818322585863799075339469173851646724567234319909755837669387 86
UVM_INFO @ 2867015411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 93058380333837445105637558753439103118872593011735469984712528795240905202491 86
UVM_INFO @ 696281968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 53720882928041480461212882874459384550027643509226504615636450734197104540957 86
UVM_INFO @ 677548280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---